CPU Execution Unit RTL Designer
Job Description
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Locations
- Austin, TX, USA
- Mountain View, CA, USA
- Portland, OR, USA
- Poughkeepsie, NY, USA
Salary
Salary not disclosed
Skills Required
- digital logic design principlesintermediate
- RTL design conceptsintermediate
- Verilog or SystemVerilogintermediate
- logic synthesis techniquesintermediate
- low-power design techniquesintermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (degree)
- 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog (experience)
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on Computer Architecture, or a related field (degree)
Responsibilities
- Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Propose performance enhancing microarchitecture features with efficiency in mind.
- Work with Architects and Performance teams for trade-off studies.
- Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
- Own design requirements for the execution unit cluster/block.
- Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.
- Deliver designs meeting Power, Performance and Area (PPA) goals with production quality.
Benefits
- bonus: Bonus included in compensation
- equity: Equity included in compensation
- general: Benefits provided by Google (details available during hiring process)
