Signal and Power Integrity Engineer
Job Description
Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team is behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Manufacturing Packaging Engineering (SMPE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Signal and Power Integrity Engineer to join the team responsible for developing advanced power delivery and signaling solutions for High Performance Computing (HPC) silicon designs. In this role, you will be responsible for driving the completion of SIPI design solutions supporting overall SOC performance interfacing with silicon, packaging, and system design teams.
Locations
- Raleigh, North Carolina, United States, Raleigh, North Carolina, United States
- Austin, Texas, United States, Austin, Texas, United States
- Boise, Idaho, United States, Boise, Idaho, United States
- Hillsboro, Oregon, United States, Hillsboro, Oregon, United States
- Redmond, Washington, United States, Redmond, Washington, United States
- Mountain View, California, United States, Mountain View, California, United States
Salary
Salary not disclosed
Required Qualifications
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. (degree)
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience (degree)
- OR equivalent experience. (degree)
- 1+ years of experience in the field of Signal and Power Integrity and delivery, System design, IP design with knowledge on product development in design and electrical modelling (degree)
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. (degree)
- Good working knowledge in the field of end to end system SIPI Design and Architecture (degree)
- Industry knowledge, trends and landscape of technologies to drive development across Silicon-IP, Advanced packaging, Substrate technology, Board technology and Platform design (degree)
- Excellent interpersonal skills including written and verbal communication, teamwork, negotiation, and presentation (degree)
- MSEE degree with 5 years’ experience in silicon packaging products development (degree)
- Experience with high-speed signal design and/or power integrity modelling for HPC products (degree)
- Strong foundation in advanced packaging technologies as it relates to Signal and Power integrity (degree)
- Experience with Foundry Silicon technologies, OSAT technologies and Substrate technologies (degree)
Preferred Qualifications
- Good working knowledge in the field of end to end system SIPI Design and Architecture (degree)
- Industry knowledge, trends and landscape of technologies to drive development across Silicon-IP, Advanced packaging, Substrate technology, Board technology and Platform design (degree)
- Excellent interpersonal skills including written and verbal communication, teamwork, negotiation, and presentation (degree)
- MSEE degree with 5 years’ experience in silicon packaging products development (degree)
- Experience with high-speed signal design and/or power integrity modelling for HPC products (degree)
- Strong foundation in advanced packaging technologies as it relates to Signal and Power integrity (degree)
- Experience with Foundry Silicon technologies, OSAT technologies and Substrate technologies (degree)
Responsibilities
- SIPI engineer for compute and AI SoCs and platforms – Implement strategies for end-to-end power delivery design and signal integrity design from Silicon to Package, and linking to Platform to System and Cloud
- Deliver SIPI solutions that meet the HPC demands across the entire system.
- Drive future power and signal integrity solutions for chiplet architecture with advanced packaging and advanced silicon nodes
- Design, model, and simulate SI and PI (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, and decoupling capacitor solution) for data center processors and corresponding platforms to ensure optimized performance. Performs DC, AC and transient simulation to provide noise, impedance profile of the whole power delivery path and link/electrical simulations to validate I/O performance from platform to silicon.
- Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.
- Drives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product lines
- Drives engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs.
Travel Requirements
3 days / week in-office
