WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a SOC Core Data Path Design Verification Engineer on AMD’s Strategic Silicon Solutions (S3) team, you will plan, create, and execute tests, testbenches, and verification environments to integrate IP blocks into complex SOC projects. You will help create custom advanced SOCs for external customers such as Sony (PlayStation 5), Microsoft (Xbox Series X), and Valve (Steam Deck) along with customers outside the game console space. You will collaborate closely with architects, design engineers, and software teams to ensure design functionality, performance, and quality for cutting-edge SOC products.   THE PERSON:  You are passionate about modern processor architecture, digital design, and SOC-level verification. You thrive in complex technical environments, are eager to understand legacy processes to improve them, and excel at problem-solving. You communicate effectively across global teams and are motivated to learn and innovate continuously.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and others to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Strong background in SOC and IP-level ASIC verification. Proficient in debugging RTL using industry-standard simulation tools. Hands-on experience with UVM-based testbenches in both Linux and Windows environments. Skilled in Verilog, SystemVerilog. Experience developing and maintaining UVM verification frameworks, test environments, and automation flows. Knowledge of distributed compute environments, workflow automation, and regression management. Familiarity with simulation profiling, acceleration, or HLS tools/processes. Strong C++ programming skills, especially on Linux; Windows exposure is a plus. Working knowledge of SystemC and TLM methodologies. Scripting experience in Perl, Ruby, Makefile, or shell. Leadership or mentorship experience is considered an asset.   ACADEMIC CREDENTIALS:  Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related discipline. LOCATION: Boxborough, MA #LI-IA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.