Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology.#ASICTWKey job responsibilities-Evaluate 3rd party IP blocks-Estimate power, performance, and area for significant IPs early in design cycle-Execute on design specifications to deliver high quality Verilog RTL-Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA-Work with pre-silicon verification teams to assist in defining test-plans/test-benches-Work with post-silicon validation teams to define and execute on test-plans-Write high quality documents to guide a scalable team
Locations
Taiwan, TPE, Hsinchu City, Hsinchu City, TPE, Taiwan
United Kingdom, Cambridge, Cambridge, England, United Kingdom
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skillsintermediate
- -Experience in Verilog digital design and debugintermediate
- -Experience with Lint, CDC and Logic Equivalencyintermediate
- -Experience with Synthesizing designsintermediate
- -Experience writing and reviewing design specificationsintermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering or a related field (degree in electrical engineering or a related field)
- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills (experience)
- -Experience in Verilog digital design and debug (experience)
- -Experience with Lint, CDC and Logic Equivalency (experience)
- -Experience with Synthesizing designs (experience)
- -Strong written and verbal skills (experience)
- -Experience writing and reviewing design specifications (experience)
Preferred Qualifications
- Master's degree in Electrical or Communications Engineering or a related field (degree in electrical or communications engineering or a related field)
Responsibilities
-Evaluate 3rd party IP blocks
-Estimate power, performance, and area for significant IPs early in design cycle
-Execute on design specifications to deliver high quality Verilog RTL
-Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA
-Work with pre-silicon verification teams to assist in defining test-plans/test-benches
-Work with post-silicon validation teams to define and execute on test-plans
-Write high quality documents to guide a scalable team
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