Design for Testability Engineer, SSG
Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production. You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more. As part of the chip design group, you will: - Contribute to the design and verification of DFT logic and components - Help to drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon - Review sign-off level timing closure using static timing analysis of DFT modes - Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis - Take high volume chips to production with high coverage ATE test program
Locations
- India, KA, Bengaluru, Bengaluru, KA, India
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skillsintermediate
- - Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testingintermediate
- - Chip design experience in Verilog and System Verilogintermediate
- - Chip verification experience, UVM methodologyintermediate
- - Top level DFT architecture definition experienceintermediate
Required Qualifications
- - Bachelor's degree in Electrical Engineering or a related field (degree in electrical engineering or a related field)
- - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills (experience)
- - Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing (experience)
- - Chip design experience in Verilog and System Verilog (experience)
- - Chip verification experience, UVM methodology (experience)
- - Scan insertion tools and methodologies (experience)
- - MBIST and BISR, BIHR insertion tools and methodologies (experience)
- - EFUSE controllers and related structures (experience)
- - Top level DFT architecture definition experience (experience)
- - Gate-level simulations (experience)
- - Static timing analysis, DFT related timing closure (experience)
- - Scripting (Perl/Tcl) (experience)
Preferred Qualifications
- - Master's degree in Electrical or Communications Engineering or a related field (degree in electrical or communications engineering or a related field)
- - Experience with formal verification techniques including abstraction and end-to-end checking (experience)
- - Experience with ARM and various DSP ISAs (experience)
- - Experience with industry standard tools and scripting languages (Python or Perl) for automation (experience)
