Sr. Physical Design Engineer - Full Chip, Hardware Compute Group
Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Roles & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs.- Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation.- Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT).- Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.- Be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.- Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).- Supervise and mentor other engineers
Locations
- India, KA, Bengaluru, Bengaluru, KA, India
Salary
Salary not disclosed
Estimated Salary Rangehigh confidence
80,000 - 180,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- - 10+ years or more of practical semiconductor implementation experienceintermediate
- - Scripting experience with Perl, Python, tcl, shell and drive to automate flowsintermediate
- - Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempusintermediate
Required Qualifications
- - Bachelor’s degree or higher in EE, CE, or CS (degree in higher in ee)
- - 10+ years or more of practical semiconductor implementation experience (experience, 10 years)
- - Scripting experience with Perl, Python, tcl, shell and drive to automate flows (experience)
- - Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus (experience)
- - Must have good communication and analytical skills. (experience)
- - Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites. (experience)
Preferred Qualifications
- - MS/PhD in Computer Science, Electrical Engineering, or related field (degree in computer science)
- - Experience with memory compiler (experience)
- - Experience with formal equivalence – Cadence Conformal/Synopsys Formality (experience)
- - Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification (experience)
- - Experience with DFT and DFM flows (experience)
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Sr. Physical Design Engineer - Full Chip, Hardware Compute Group
Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Roles & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs.- Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation.- Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT).- Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.- Be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.- Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).- Supervise and mentor other engineers
Locations
- India, KA, Bengaluru, Bengaluru, KA, India
Salary
Salary not disclosed
Estimated Salary Rangehigh confidence
80,000 - 180,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- - 10+ years or more of practical semiconductor implementation experienceintermediate
- - Scripting experience with Perl, Python, tcl, shell and drive to automate flowsintermediate
- - Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempusintermediate
Required Qualifications
- - Bachelor’s degree or higher in EE, CE, or CS (degree in higher in ee)
- - 10+ years or more of practical semiconductor implementation experience (experience, 10 years)
- - Scripting experience with Perl, Python, tcl, shell and drive to automate flows (experience)
- - Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus (experience)
- - Must have good communication and analytical skills. (experience)
- - Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites. (experience)
Preferred Qualifications
- - MS/PhD in Computer Science, Electrical Engineering, or related field (degree in computer science)
- - Experience with memory compiler (experience)
- - Experience with formal equivalence – Cadence Conformal/Synopsys Formality (experience)
- - Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification (experience)
- - Experience with DFT and DFM flows (experience)