Sr. RFIC Layout Design Engineer, Project Kuiper
Job Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Role for Kuiper Sr. RFIC Layout design engineer:As a Sr. RFIC Layout design engineer, you will be an integral part of the IC design team. Lead layout at a technical level, build circuit layouts for RF controller architectures. You will work in an integral team with the RFIC/Mixed signal designers on full chip layout of custom analog and RFIC designs. Work with the IC designers and chip leads to determine the chip floor plan. This includes strategies for power and ground distribution as well as working with package engineers to determine pad locations. You are required to accurately estimating the schedule for the layout tasks in a timely manner that is trackable, reportable and in sync with project deliverables. You are to identifying areas of complexity that needs early investigation.Perform custom layout of RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout. Requirements include proficiency in Cadence Software (EDA) to develop, test and improve manufacturing processes and product designs for analog circuits. Proficiency in DRCs, ERCs and LVS checks; and resolving errors. Proficiency top-level layout integration with ESD structures and pad assembly; Including density fill, running DFM checks, preparing database for foundry deliveryExport Control Requirement:Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.Key job responsibilitiesIn this role you will:• You will work closely with an internal inter-disciplinary team to drive key aspects of product definition, execution and optimization. • You must be responsive, flexible and able to succeed within an open collaborative peer environment.• You are required to specialize in application-specific integrated circuits. Additional requirements include proficiency/expertise in Cadence Software (CAD) to develop, test and improve manufacturing processes and product designs for analog circuits. • Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are necessary. • Perform checks such as multi-patterning, latch-up, ESD, and density• Required to perform layout in a timely manner that is trackable, reportable and in sync with project schedule• Collaborate with digital design, and other RFIC design teams to define floorplans for RF front-ends and beamforming ICs.• Layout high-performance analog, RF and mm-wave circuits keeping in mind requirements for matching, parasitic capacitance, electromigration, and all DRC rules.
Locations
- United States, WA, Redmond, Redmond, WA, United States
- United States, CA, San Diego, San Diego, CA, United States
Salary
Salary not disclosed
Estimated Salary Rangehigh confidence
180,000 - 250,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- • Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experienceintermediate
- • 7+ years of hands on experience full-custom analog or RF layout for high performance chipsintermediate
Required Qualifications
- • Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience (experience)
- • 7+ years of hands on experience full-custom analog or RF layout for high performance chips (experience, 7 years)
- • Proven track record where products have gone to volume production a plus (experience)
Preferred Qualifications
- • Bachelor’s degree in Electrical Engineering or other technical field (degree in electrical engineering or other technical field)
- • 10+ years in full-custom analog or RF layout for high performance chips (experience, 10 years)
- • Experience maintaining EAD tools for DRC, LVS, RC extraction, and design database management. (experience)
- • Experience writing or modifying DRC rules files; a plus (experience)
- • Strong written and verbal skills (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
- Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site. (experience)
Responsibilities
- In this role you will:
- • You will work closely with an internal inter-disciplinary team to drive key aspects of product definition, execution and optimization.
- • You must be responsive, flexible and able to succeed within an open collaborative peer environment.
- • You are required to specialize in application-specific integrated circuits. Additional requirements include proficiency/expertise in Cadence Software (CAD) to develop, test and improve manufacturing processes and product designs for analog circuits.
- • Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are necessary.
- • Perform checks such as multi-patterning, latch-up, ESD, and density
- • Required to perform layout in a timely manner that is trackable, reportable and in sync with project schedule
- • Collaborate with digital design, and other RFIC design teams to define floorplans for RF front-ends and beamforming ICs.
- • Layout high-performance analog, RF and mm-wave circuits keeping in mind requirements for matching, parasitic capacitance, electromigration, and all DRC rules.
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Sr. RFIC Layout Design Engineer, Project Kuiper
Job Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Role for Kuiper Sr. RFIC Layout design engineer:As a Sr. RFIC Layout design engineer, you will be an integral part of the IC design team. Lead layout at a technical level, build circuit layouts for RF controller architectures. You will work in an integral team with the RFIC/Mixed signal designers on full chip layout of custom analog and RFIC designs. Work with the IC designers and chip leads to determine the chip floor plan. This includes strategies for power and ground distribution as well as working with package engineers to determine pad locations. You are required to accurately estimating the schedule for the layout tasks in a timely manner that is trackable, reportable and in sync with project deliverables. You are to identifying areas of complexity that needs early investigation.Perform custom layout of RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout. Requirements include proficiency in Cadence Software (EDA) to develop, test and improve manufacturing processes and product designs for analog circuits. Proficiency in DRCs, ERCs and LVS checks; and resolving errors. Proficiency top-level layout integration with ESD structures and pad assembly; Including density fill, running DFM checks, preparing database for foundry deliveryExport Control Requirement:Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.Key job responsibilitiesIn this role you will:• You will work closely with an internal inter-disciplinary team to drive key aspects of product definition, execution and optimization. • You must be responsive, flexible and able to succeed within an open collaborative peer environment.• You are required to specialize in application-specific integrated circuits. Additional requirements include proficiency/expertise in Cadence Software (CAD) to develop, test and improve manufacturing processes and product designs for analog circuits. • Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are necessary. • Perform checks such as multi-patterning, latch-up, ESD, and density• Required to perform layout in a timely manner that is trackable, reportable and in sync with project schedule• Collaborate with digital design, and other RFIC design teams to define floorplans for RF front-ends and beamforming ICs.• Layout high-performance analog, RF and mm-wave circuits keeping in mind requirements for matching, parasitic capacitance, electromigration, and all DRC rules.
Locations
- United States, WA, Redmond, Redmond, WA, United States
- United States, CA, San Diego, San Diego, CA, United States
Salary
Salary not disclosed
Estimated Salary Rangehigh confidence
180,000 - 250,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- • Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experienceintermediate
- • 7+ years of hands on experience full-custom analog or RF layout for high performance chipsintermediate
Required Qualifications
- • Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience (experience)
- • 7+ years of hands on experience full-custom analog or RF layout for high performance chips (experience, 7 years)
- • Proven track record where products have gone to volume production a plus (experience)
Preferred Qualifications
- • Bachelor’s degree in Electrical Engineering or other technical field (degree in electrical engineering or other technical field)
- • 10+ years in full-custom analog or RF layout for high performance chips (experience, 10 years)
- • Experience maintaining EAD tools for DRC, LVS, RC extraction, and design database management. (experience)
- • Experience writing or modifying DRC rules files; a plus (experience)
- • Strong written and verbal skills (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
- Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site. (experience)
Responsibilities
- In this role you will:
- • You will work closely with an internal inter-disciplinary team to drive key aspects of product definition, execution and optimization.
- • You must be responsive, flexible and able to succeed within an open collaborative peer environment.
- • You are required to specialize in application-specific integrated circuits. Additional requirements include proficiency/expertise in Cadence Software (CAD) to develop, test and improve manufacturing processes and product designs for analog circuits.
- • Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are necessary.
- • Perform checks such as multi-patterning, latch-up, ESD, and density
- • Required to perform layout in a timely manner that is trackable, reportable and in sync with project schedule
- • Collaborate with digital design, and other RFIC design teams to define floorplans for RF front-ends and beamforming ICs.
- • Layout high-performance analog, RF and mm-wave circuits keeping in mind requirements for matching, parasitic capacitance, electromigration, and all DRC rules.