Sr. Verification Engineer, Amazon Camera ASIC Team
Job Description
Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Drive early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the time to revenue. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology.Key job responsibilities- Define architecture specifications based on requirements from product teams- Create microarchitecture specifications suitable for being implemented by junior engineers- Evaluate 3rd party IP blocks- Estimate power, performance, and area for significant IPs early in design cycle- Execute on design specifications to deliver high quality RTL- Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA- Take the lead and work with verification teams to define functional coverage- Work with pre-silicon verification teams to assist in defining testplans/testbenches- Work with post-silicon validation teams to define and execute on testplans- Write high quality documents to guide and lead a scalable team
Locations
- United Kingdom, Cambridge, Cambridge, England, United Kingdom
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
85,000 - 120,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- - Experience building complex UVM components, traffic generators and scoreboardsintermediate
- - Experience in architecting and building block, cluster and system level testbenchesintermediate
- - System Verilog experience and senior level debug skills.intermediate
- - Experience in leading full chip or complex IP development from architecture through T/Ointermediate
Required Qualifications
- - Bachelor's degree in Electrical Engineering or a related field (degree in electrical engineering or a related field)
- - Experience building complex UVM components, traffic generators and scoreboards (experience)
- - Experience in architecting and building block, cluster and system level testbenches (experience)
- - System Verilog experience and senior level debug skills. (experience)
- - Experience in leading full chip or complex IP development from architecture through T/O (experience)
Preferred Qualifications
- - Master's degree or Ph.D. degree in Electrical Engineering or related field (degree in ph)
- - Experience with formal verification techniques including abstraction and end-to-end checking (experience)
- - Extensive experience in digital design (experience)
- - Experience with physical implementation flows (experience)
Responsibilities
- - Define architecture specifications based on requirements from product teams
- - Create microarchitecture specifications suitable for being implemented by junior engineers
- - Evaluate 3rd party IP blocks
- - Estimate power, performance, and area for significant IPs early in design cycle
- - Execute on design specifications to deliver high quality RTL
- - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA
- - Take the lead and work with verification teams to define functional coverage
- - Work with pre-silicon verification teams to assist in defining testplans/testbenches
- - Work with post-silicon validation teams to define and execute on testplans
- - Write high quality documents to guide and lead a scalable team
Documents
Application Instructions
https://www.amazon.jobs/en/jobs/3115263