Associate Engineer, Physical Design Engineering Careers at Analog Devices in San Jose, California | Launch Your VLSI Career
Overview: Powering the Intelligent Edge with Cutting-Edge Physical Design
Imagine contributing to the silicon that powers autonomous vehicles, AI data centers, and next-generation connectivity solutions. At Analog Devices in San Jose, California, our Associate Engineer, Physical Design Engineering role offers new college graduates the opportunity to dive into advanced-node ASIC implementation for eFPGA intellectual property that drives industry transformation. With over 55 years of breakthrough innovation, Analog Devices bridges the physical and digital worlds, enabling $9+ billion in annual revenue through solutions in digitized factories, mobility, digital healthcare, and climate initiatives.
This graduate position immerses you in the full ASIC backend flow—from RTL handoff through GDSII tapeout—working on bleeding-edge 16nm, 5nm, and 4nm processes. You'll collaborate with world-class front-end design, verification, architecture, low-power, and packaging teams to deliver production-quality silicon that powers the Intelligent Edge. San Jose's Silicon Valley epicenter provides unmatched proximity to semiconductor innovation hubs, EDA tool developers, and fab partners, accelerating your professional growth in Physical Design Engineering.
Physical Design at Analog Devices isn't just implementation; it's strategic optimization balancing power-performance-area (PPA) tradeoffs for AI accelerators, high-speed connectivity, and embedded FPGA applications. As an Associate Engineer, you'll gain hands-on mastery of industry-standard EDA flows while contributing to real tapeouts that ship in volume. This role demands analytical precision, scripting prowess, and collaborative problem-solving—skills that position you for rapid advancement in VLSI leadership.
A Day in the Life of a Physical Design Engineer at Analog Devices San Jose
Your morning begins with a standup review of overnight regression runs, analyzing timing paths and congestion hotspots across multi-corner multi-mode ( MCMM ) scenarios. Diving into Cadence Innovus, you refine floorplans for a 5nm eFPGA block, balancing macro placement with standard cell density while meeting power budget constraints. Mid-morning brings collaboration with the RTL team to resolve synthesis handoff issues, scripting Tcl automation to regenerate timing constraints.
Lunch in San Jose's vibrant downtown connects you with peers from verification and architecture, exchanging insights on low-power UPF implementation. Afternoon focuses on clock tree synthesis optimization, iterating PrimeTime STA reports to close critical paths under 100ps skew targets. You debug IR-drop violations using Ansys RedHawk, implementing decap strategies and power grid enhancements. As ECO season approaches, Python scripts streamline engineering change order propagation, ensuring DRC/LVS clean tapeout readiness.
Cross-functional reviews with packaging engineers address signal integrity and thermal concerns, while documentation captures flow improvements for team knowledge sharing. Evenings might involve 10% travel to fab partners or customer sites, but flexible work options and San Jose's traffic-optimized campus make work-life balance achievable. This dynamic rhythm builds expertise across the Physical Design spectrum, preparing you for senior roles within 2-3 years.
Why San Jose, California? Silicon Valley's Premier Semiconductor Destination
San Jose anchors Silicon Valley's semiconductor ecosystem, hosting Cadence, Synopsys, NVIDIA, and countless fabless innovators. Analog Devices' state-of-the-art facility leverages proximity to EDA headquarters (5 miles from Cadence), ensuring direct tool feedback loops and early access to flows. The region's 300+ sunny days, diverse cuisine from Japantown to Santana Row, and tech talent density create an unparalleled professional environment.
Rio Robles, California offers a quieter alternative with easy Bay Area access, combining suburban quality of life with cutting-edge engineering. Both locations benefit from California's innovation tax credits, world-class universities (Stanford, UC Berkeley), and semiconductor supply chain concentration. San Jose's median home values reflect premium talent markets, but Analog Devices' competitive compensation offsets living costs while delivering equity upside in a NASDAQ: ADI powerhouse.
Beyond work, San Jose's 75+ parks, Winchester Mystery House, and tech conference scene (DAC, Hot Chips) enrich life. Public transit, electric vehicle infrastructure, and remote collaboration tools minimize commutes, maximizing impact on global semiconductor advancement.
Career Growth Trajectory in Physical Design at Analog Devices
Analog Devices invests heavily in graduate development, pairing you with senior mentors for weekly 1:1s and rotation opportunities across eFPGA, mixed-signal, and AI accelerator projects. Within 12 months, you'll lead block-level tapeouts; by year two, own chip-level flows. Technical tracks advance to Staff Physical Design Engineer ($150K+), while management paths lead to Engineering Manager roles overseeing 10+ engineers.
Continuous learning includes EDA vendor training, internal VLSI bootcamps, and tuition reimbursement for MSEE/PhD programs. 10% travel exposes you to Taiwan fabs and customer design wins, broadening global perspective. Performance-based promotion cycles (twice yearly) reward PPA improvements, automation contributions, and cross-team leadership—fast-tracking top performers to Principal Engineer within 5 years.
Rewards: Compensation, Benefits, and Professional Fulfillment
Base salary ranges $86,043-$118,309, varying by experience and location, plus discretionary bonuses tied to tapeout success and company performance. Comprehensive benefits include medical/vision/dental, 401k match, unlimited PTO accrual, 10+ holidays, and family leave. Flexible hybrid models accommodate San Jose's dynamic lifestyle.
Equity grants vest over 4 years, aligning you with ADI's growth trajectory. Professional rewards extend beyond compensation—contributing to shipped silicon powering millions of devices delivers unmatched impact. Sustainable practices, DEI initiatives, and employee resource groups foster belonging in a 24,000-person global leader.
ADI Culture: Innovation, Collaboration, Continuous Learning
Analog Devices cultivates psychological safety where engineers challenge assumptions and propose bold flows. Cross-functional pods dissolve silos, with architecture, verification, and physical design co-located for real-time iteration. Hack weeks encourage scripting innovations; patent incentives reward novel optimization algorithms.
Sustainability integrates into design—low-power flows combat climate change while enabling energy-efficient edge computing. DEI metrics track representation; employee networks support women in tech, veterans, and underrepresented groups. Ahead of What's Possible™ isn't marketing—it's daily reality for Physical Design Engineers shaping semiconductor's future.
Apply Now: Your Path to Physical Design Excellence
Ready to implement silicon that transforms industries? Submit your resume highlighting VLSI coursework, EDA projects, and scripting experience. Include GitHub links to automation flows or academic tapeouts. Analog Devices' streamlined process includes technical screening, EDA practical, and team interviews—all virtual initially.
U.S. export compliance applies; citizens/permanent residents expedited. EEO employer prioritizing diverse talent. Join 24,000 innovators ensuring tomorrow's breakthroughs start with your Physical Design expertise today.
