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Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now

Analog Devices

Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now

full-timePosted: Jan 28, 2026

Job Description

Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain

Overview

Analog Devices stands at the forefront of semiconductor innovation, bridging the physical and digital worlds to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and human connectivity. In Valencia, Cortes Valencianas, Spain, our Physical Design Engineer role within the Consumer Sensing Solutions (CSS) team offers a pivotal opportunity to shape next-generation consumer products featuring capacitive sensing, optical image stabilization, and advanced optical sensing technologies.

This position immerses you in developing mixed-signal subsystems for cutting-edge consumer chips, combining digital signal processing, embedded microprocessors, and high-precision analog blocks. Located in vibrant Valencia, you'll leverage state-of-the-art physical design methodologies on 40nm processes, gaining exposure to diverse technical domains while driving sustainable growth in our portable consumer business. Join a highly motivated team committed to continuous career development and market leadership.

Valencia's thriving tech ecosystem, Mediterranean lifestyle, and Analog Devices' world-class facilities create the perfect environment for engineering excellence. With 10% travel and 1st shift hours, this role balances professional challenges with personal fulfillment in one of Spain's most dynamic cities.

A Day in the Life of a Physical Design Engineer

Your day begins at 9 AM in our modern Valencia office, overlooking the Turia Gardens. After coffee with colleagues from Ireland and the US, you dive into floorplanning a complex mixed-signal SoC. Using Cadence Innovus, you optimize power grid distribution while collaborating via Slack with RTL designers on timing constraints.

By 11 AM, you're running synthesis with Genus, scripting Tcl automations to handle multi-mode STA. Lunch features paella from the onsite cafeteria, followed by clock tree synthesis reviews. Afternoon brings place-and-route iterations, power analysis with Voltus, and DRC/LVS verification. You resolve an ECO from the analog team, ensuring seamless mixed-signal integration.

Ending with a standup call tracking project milestones, you wrap up by 6 PM, often joining team volleyball or exploring Valencia's beaches. This rhythm blends deep technical work with global collaboration and Spanish work-life harmony.

Why Valencia, Cortes Valencianas?

Valencia, the third-largest city in Spain, captivates with its perfect blend of innovation, culture, and lifestyle. Home to the City of Arts and Sciences, Europe's largest aquarium, and a booming tech scene, it attracts global talent. Our Valencia office sits in the cutting-edge Fuente de San Luis district, minutes from high-speed rail to Madrid and Barcelona.

Cortes Valencianas offers 300+ sunny days yearly, pristine Mediterranean beaches like Malvarrosa, and UNESCO-protected historic centers. Tech hubs like Marina Real Juan Carlos I foster semiconductor innovation, while lower living costs than Barcelona or Madrid maximize your salary. Excellent international schools, bilingual environment, and Valencia Airport's global connections make relocation seamless.

Spain's supportive expat policies, EU mobility, and vibrant food scene—from fresh seafood to Michelin-starred paella—enhance life quality. Analog Devices leverages Valencia's engineering talent pool from Universitat Politècnica de València, creating a collaborative ecosystem unmatched in Europe.

Career Growth Opportunities

Analog Devices invests heavily in your professional evolution. As Physical Design Engineer, you'll progress from individual contributor to technical lead within 2-3 years, owning full chip implementations. Our CSS team offers cross-functional exposure to consumer, automotive, and industrial domains.

Mentorship from 20+ year veterans, technical ladders to Principal Engineer (€150K+), and management tracks await top performers. Annual development budgets fund Cadence certifications, IEEE conferences, and advanced node training. Global rotation programs to Limerick, Ireland or Wilmington, Massachusetts broaden perspectives.

With 24,000 employees worldwide, internal mobility spans 50+ locations. 70% of leadership roles fill internally, backed by our Ahead of What's Possible™ philosophy ensuring continuous innovation and advancement.

Rewards and Compensation

We offer competitive €65,000-€95,000 base salary (10+ years experience), 20% performance bonus, and RSU grants. Comprehensive benefits include private health/dental coverage, 24 vacation days, flexible hours, hybrid work, and pension matching. Relocation packages cover housing, visas, and Spanish lessons.

Wellness perks feature gym subsidies, EAP counseling, and sustainable transport allowances. Parental leave exceeds Spanish mandates at 20 weeks fully paid. Professional growth includes €5,000 annual training budget and conference travel. In Valencia's affordable market, your compensation stretches further, enabling beachfront living and European adventures.

Company Culture at Analog Devices

Our culture champions innovation, inclusion, and impact. #AheadOfWhatsPossible drives daily breakthroughs while Diversity, Equity, Inclusion initiatives ensure everyone thrives regardless of background. Valencia's team embodies Spanish warmth with global professionalism—weekly tapas Fridays, volleyball leagues, and hackathons build camaraderie.

Flat hierarchies empower ownership; your ideas shape tapeouts serving billions. Sustainability commitments include net-zero goals and green campuses. With 10% travel fostering global bonds, you'll collaborate seamlessly across time zones, supported by cutting-edge tools and zero politics.

How to Apply

Ready to advance semiconductor frontiers in Valencia? Submit your CV highlighting 40nm experience, Cadence tools, and scripting prowess. Include GitHub repos or tapeout portfolios. Our talent team reviews applications weekly, with interviews featuring technical deep-dives, behavioral panels, and culture fit discussions.

Timeline: 1 week screening, 2 weeks interviews, immediate offers for top candidates. EU citizens prioritized; sponsorship available for exceptional talent. Join us—apply now and stay Ahead of What's Possible™.

FAQ

What experience level is required?

10+ years in digital physical design, with essential 40nm implementation experience.

Is visa sponsorship available?

Yes, for exceptional candidates. EU citizens prioritized.

What tools does the team use?

Cadence Innovus, Genus, Virtuoso, Voltus primary; Synopsys flows secondary.

Is hybrid work available?

Yes, 3 days office, 2 remote after onboarding.

What's the team structure?

15 engineers in Valencia + global CSS team across Ireland, US, Asia.

Locations

  • Valencia, Cortes Valencianas, Spain

Salary

65,000 - 95,000 EUR / yearly

Estimated Salary Rangehigh confidence

65,000 - 95,000 EUR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Floor planning and power/ground distributionintermediate
  • Place and route methodologiesintermediate
  • Clock Tree Synthesis (CTS)intermediate
  • Static Timing Analysis (STA)intermediate
  • ECO implementation and timing closureintermediate
  • Power analysis and optimizationintermediate
  • Physical design verification (LVS, DRC)intermediate
  • Logic synthesis and timing constraintsintermediate
  • Scripting in Tcl, SKILL, Perlintermediate
  • Cadence implementation tools (Innovus, Genus)intermediate
  • Cadence Virtuoso for layoutintermediate
  • Perforce/Methodics version controlintermediate
  • CPF/UPF power intent handlingintermediate
  • 40nm and advanced node experienceintermediate
  • GDS2 tapeout processesintermediate
  • Foundry rule complianceintermediate
  • RTL-to-GDSII flow ownershipintermediate
  • Cross-functional team collaborationintermediate
  • Geographically distributed teamworkintermediate
  • Technical problem-solvingintermediate
  • Schedule development and trackingintermediate
  • Digital subsystem deliveryintermediate
  • Mixed-signal integrationintermediate
  • High-precision analog interfacingintermediate

Required Qualifications

  • B.Tech/M.Tech in Electrical Engineering or ECE (experience)
  • 10+ years in digital physical implementation (experience)
  • Strong floorplanning expertise (experience)
  • Proven place & route experience (experience)
  • Clock Tree Synthesis proficiency (experience)
  • Static Timing Analysis mastery (experience)
  • ECO methodology knowledge (experience)
  • Power analysis skills (experience)
  • Physical verification expertise (experience)
  • Synthesis and timing constraints (experience)
  • 40nm node implementation essential (experience)
  • Tcl, SKILL, Perl scripting (experience)
  • Cadence tools preferred (experience)
  • Perforce/Methodics experience (experience)
  • CPF/UPF advantage (experience)
  • Cadence Virtuoso knowledge (experience)
  • Foundry rules and GDS2 tapeout (experience)
  • Technical ownership capability (experience)
  • Hands-on implementation responsibility (experience)
  • Strong interpersonal skills (experience)
  • Teamwork and communication (experience)
  • Mixed-signal subsystem experience (experience)
  • Consumer product development background (experience)

Responsibilities

  • Develop floorplans for complex SoCs
  • Design power/ground distribution networks
  • Implement clock distribution trees
  • Execute logic synthesis flows
  • Perform cell placement optimization
  • Route interconnects for timing closure
  • Conduct equivalence checking
  • Achieve timing closure across modes
  • Run physical verification (LVS/DRC)
  • Collaborate with RTL design teams
  • Solve challenging timing issues
  • Own delivery of digital subsystems
  • Develop project schedules
  • Monitor implementation progress
  • Work with global engineering teams
  • Integrate mixed-signal subsystems
  • Optimize power consumption
  • Handle ECO implementations
  • Generate tapeout-ready GDSII
  • Script automation for flows
  • Ensure foundry rule compliance
  • Document design methodologies

Benefits

  • general: Competitive base salary €65,000-€95,000
  • general: Annual performance bonus up to 20%
  • general: Comprehensive health insurance
  • general: Dental and vision coverage
  • general: 401(k) matching (US) / Pension (EU)
  • general: Stock purchase plan with discount
  • general: 24+ vacation days annually
  • general: Flexible working hours
  • general: Hybrid work model available
  • general: Professional development budget
  • general: Tuition reimbursement program
  • general: On-site fitness facilities
  • general: Employee assistance program
  • general: Parental leave (16+ weeks)
  • general: Wellness programs and gym membership
  • general: Relocation assistance package
  • general: Technical conference attendance
  • general: Mentorship programs
  • general: Career growth opportunities
  • general: Team building events
  • general: Modern office in Valencia
  • general: Free snacks and beverages
  • general: Sustainable commuting benefits

Target Your Resume for "Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now" , Analog Devices

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Tags & Categories

Physical Design EngineerAnalog Devices careersValencia Spain jobsCortes Valencianas engineering40nm physical implementationCadence Innovus jobsMixed-signal SoC designDigital place and routeClock Tree SynthesisStatic Timing AnalysisSemiconductor jobs SpainPhysical verification engineerGDSII tapeout specialistTcl Perl scripting jobsConsumer electronics ICOptical sensing designCapacitive sensing engineerPower analysis VoltusRTL to GDSII flowEngineering jobs ValenciaAnalog Devices ValenciaSpain tech careersPhysical design CadenceEngineeringSemiconductorsPhysical DesignIC DesignSpain Jobs

Answer 10 quick questions to check your fit for Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now @ Analog Devices.

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Analog Devices logo

Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now

Analog Devices

Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now

full-timePosted: Jan 28, 2026

Job Description

Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain

Overview

Analog Devices stands at the forefront of semiconductor innovation, bridging the physical and digital worlds to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and human connectivity. In Valencia, Cortes Valencianas, Spain, our Physical Design Engineer role within the Consumer Sensing Solutions (CSS) team offers a pivotal opportunity to shape next-generation consumer products featuring capacitive sensing, optical image stabilization, and advanced optical sensing technologies.

This position immerses you in developing mixed-signal subsystems for cutting-edge consumer chips, combining digital signal processing, embedded microprocessors, and high-precision analog blocks. Located in vibrant Valencia, you'll leverage state-of-the-art physical design methodologies on 40nm processes, gaining exposure to diverse technical domains while driving sustainable growth in our portable consumer business. Join a highly motivated team committed to continuous career development and market leadership.

Valencia's thriving tech ecosystem, Mediterranean lifestyle, and Analog Devices' world-class facilities create the perfect environment for engineering excellence. With 10% travel and 1st shift hours, this role balances professional challenges with personal fulfillment in one of Spain's most dynamic cities.

A Day in the Life of a Physical Design Engineer

Your day begins at 9 AM in our modern Valencia office, overlooking the Turia Gardens. After coffee with colleagues from Ireland and the US, you dive into floorplanning a complex mixed-signal SoC. Using Cadence Innovus, you optimize power grid distribution while collaborating via Slack with RTL designers on timing constraints.

By 11 AM, you're running synthesis with Genus, scripting Tcl automations to handle multi-mode STA. Lunch features paella from the onsite cafeteria, followed by clock tree synthesis reviews. Afternoon brings place-and-route iterations, power analysis with Voltus, and DRC/LVS verification. You resolve an ECO from the analog team, ensuring seamless mixed-signal integration.

Ending with a standup call tracking project milestones, you wrap up by 6 PM, often joining team volleyball or exploring Valencia's beaches. This rhythm blends deep technical work with global collaboration and Spanish work-life harmony.

Why Valencia, Cortes Valencianas?

Valencia, the third-largest city in Spain, captivates with its perfect blend of innovation, culture, and lifestyle. Home to the City of Arts and Sciences, Europe's largest aquarium, and a booming tech scene, it attracts global talent. Our Valencia office sits in the cutting-edge Fuente de San Luis district, minutes from high-speed rail to Madrid and Barcelona.

Cortes Valencianas offers 300+ sunny days yearly, pristine Mediterranean beaches like Malvarrosa, and UNESCO-protected historic centers. Tech hubs like Marina Real Juan Carlos I foster semiconductor innovation, while lower living costs than Barcelona or Madrid maximize your salary. Excellent international schools, bilingual environment, and Valencia Airport's global connections make relocation seamless.

Spain's supportive expat policies, EU mobility, and vibrant food scene—from fresh seafood to Michelin-starred paella—enhance life quality. Analog Devices leverages Valencia's engineering talent pool from Universitat Politècnica de València, creating a collaborative ecosystem unmatched in Europe.

Career Growth Opportunities

Analog Devices invests heavily in your professional evolution. As Physical Design Engineer, you'll progress from individual contributor to technical lead within 2-3 years, owning full chip implementations. Our CSS team offers cross-functional exposure to consumer, automotive, and industrial domains.

Mentorship from 20+ year veterans, technical ladders to Principal Engineer (€150K+), and management tracks await top performers. Annual development budgets fund Cadence certifications, IEEE conferences, and advanced node training. Global rotation programs to Limerick, Ireland or Wilmington, Massachusetts broaden perspectives.

With 24,000 employees worldwide, internal mobility spans 50+ locations. 70% of leadership roles fill internally, backed by our Ahead of What's Possible™ philosophy ensuring continuous innovation and advancement.

Rewards and Compensation

We offer competitive €65,000-€95,000 base salary (10+ years experience), 20% performance bonus, and RSU grants. Comprehensive benefits include private health/dental coverage, 24 vacation days, flexible hours, hybrid work, and pension matching. Relocation packages cover housing, visas, and Spanish lessons.

Wellness perks feature gym subsidies, EAP counseling, and sustainable transport allowances. Parental leave exceeds Spanish mandates at 20 weeks fully paid. Professional growth includes €5,000 annual training budget and conference travel. In Valencia's affordable market, your compensation stretches further, enabling beachfront living and European adventures.

Company Culture at Analog Devices

Our culture champions innovation, inclusion, and impact. #AheadOfWhatsPossible drives daily breakthroughs while Diversity, Equity, Inclusion initiatives ensure everyone thrives regardless of background. Valencia's team embodies Spanish warmth with global professionalism—weekly tapas Fridays, volleyball leagues, and hackathons build camaraderie.

Flat hierarchies empower ownership; your ideas shape tapeouts serving billions. Sustainability commitments include net-zero goals and green campuses. With 10% travel fostering global bonds, you'll collaborate seamlessly across time zones, supported by cutting-edge tools and zero politics.

How to Apply

Ready to advance semiconductor frontiers in Valencia? Submit your CV highlighting 40nm experience, Cadence tools, and scripting prowess. Include GitHub repos or tapeout portfolios. Our talent team reviews applications weekly, with interviews featuring technical deep-dives, behavioral panels, and culture fit discussions.

Timeline: 1 week screening, 2 weeks interviews, immediate offers for top candidates. EU citizens prioritized; sponsorship available for exceptional talent. Join us—apply now and stay Ahead of What's Possible™.

FAQ

What experience level is required?

10+ years in digital physical design, with essential 40nm implementation experience.

Is visa sponsorship available?

Yes, for exceptional candidates. EU citizens prioritized.

What tools does the team use?

Cadence Innovus, Genus, Virtuoso, Voltus primary; Synopsys flows secondary.

Is hybrid work available?

Yes, 3 days office, 2 remote after onboarding.

What's the team structure?

15 engineers in Valencia + global CSS team across Ireland, US, Asia.

Locations

  • Valencia, Cortes Valencianas, Spain

Salary

65,000 - 95,000 EUR / yearly

Estimated Salary Rangehigh confidence

65,000 - 95,000 EUR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Floor planning and power/ground distributionintermediate
  • Place and route methodologiesintermediate
  • Clock Tree Synthesis (CTS)intermediate
  • Static Timing Analysis (STA)intermediate
  • ECO implementation and timing closureintermediate
  • Power analysis and optimizationintermediate
  • Physical design verification (LVS, DRC)intermediate
  • Logic synthesis and timing constraintsintermediate
  • Scripting in Tcl, SKILL, Perlintermediate
  • Cadence implementation tools (Innovus, Genus)intermediate
  • Cadence Virtuoso for layoutintermediate
  • Perforce/Methodics version controlintermediate
  • CPF/UPF power intent handlingintermediate
  • 40nm and advanced node experienceintermediate
  • GDS2 tapeout processesintermediate
  • Foundry rule complianceintermediate
  • RTL-to-GDSII flow ownershipintermediate
  • Cross-functional team collaborationintermediate
  • Geographically distributed teamworkintermediate
  • Technical problem-solvingintermediate
  • Schedule development and trackingintermediate
  • Digital subsystem deliveryintermediate
  • Mixed-signal integrationintermediate
  • High-precision analog interfacingintermediate

Required Qualifications

  • B.Tech/M.Tech in Electrical Engineering or ECE (experience)
  • 10+ years in digital physical implementation (experience)
  • Strong floorplanning expertise (experience)
  • Proven place & route experience (experience)
  • Clock Tree Synthesis proficiency (experience)
  • Static Timing Analysis mastery (experience)
  • ECO methodology knowledge (experience)
  • Power analysis skills (experience)
  • Physical verification expertise (experience)
  • Synthesis and timing constraints (experience)
  • 40nm node implementation essential (experience)
  • Tcl, SKILL, Perl scripting (experience)
  • Cadence tools preferred (experience)
  • Perforce/Methodics experience (experience)
  • CPF/UPF advantage (experience)
  • Cadence Virtuoso knowledge (experience)
  • Foundry rules and GDS2 tapeout (experience)
  • Technical ownership capability (experience)
  • Hands-on implementation responsibility (experience)
  • Strong interpersonal skills (experience)
  • Teamwork and communication (experience)
  • Mixed-signal subsystem experience (experience)
  • Consumer product development background (experience)

Responsibilities

  • Develop floorplans for complex SoCs
  • Design power/ground distribution networks
  • Implement clock distribution trees
  • Execute logic synthesis flows
  • Perform cell placement optimization
  • Route interconnects for timing closure
  • Conduct equivalence checking
  • Achieve timing closure across modes
  • Run physical verification (LVS/DRC)
  • Collaborate with RTL design teams
  • Solve challenging timing issues
  • Own delivery of digital subsystems
  • Develop project schedules
  • Monitor implementation progress
  • Work with global engineering teams
  • Integrate mixed-signal subsystems
  • Optimize power consumption
  • Handle ECO implementations
  • Generate tapeout-ready GDSII
  • Script automation for flows
  • Ensure foundry rule compliance
  • Document design methodologies

Benefits

  • general: Competitive base salary €65,000-€95,000
  • general: Annual performance bonus up to 20%
  • general: Comprehensive health insurance
  • general: Dental and vision coverage
  • general: 401(k) matching (US) / Pension (EU)
  • general: Stock purchase plan with discount
  • general: 24+ vacation days annually
  • general: Flexible working hours
  • general: Hybrid work model available
  • general: Professional development budget
  • general: Tuition reimbursement program
  • general: On-site fitness facilities
  • general: Employee assistance program
  • general: Parental leave (16+ weeks)
  • general: Wellness programs and gym membership
  • general: Relocation assistance package
  • general: Technical conference attendance
  • general: Mentorship programs
  • general: Career growth opportunities
  • general: Team building events
  • general: Modern office in Valencia
  • general: Free snacks and beverages
  • general: Sustainable commuting benefits

Target Your Resume for "Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now" , Analog Devices

Get personalized recommendations to optimize your resume specifically for Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now" , Analog Devices

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Physical Design EngineerAnalog Devices careersValencia Spain jobsCortes Valencianas engineering40nm physical implementationCadence Innovus jobsMixed-signal SoC designDigital place and routeClock Tree SynthesisStatic Timing AnalysisSemiconductor jobs SpainPhysical verification engineerGDSII tapeout specialistTcl Perl scripting jobsConsumer electronics ICOptical sensing designCapacitive sensing engineerPower analysis VoltusRTL to GDSII flowEngineering jobs ValenciaAnalog Devices ValenciaSpain tech careersPhysical design CadenceEngineeringSemiconductorsPhysical DesignIC DesignSpain Jobs

Answer 10 quick questions to check your fit for Physical Design Engineer Careers at Analog Devices in Valencia, Cortes Valencianas, Spain | Apply Now @ Analog Devices.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.