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Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Principal DFT Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading DFT Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and seamless connectivity. In Bangalore, India – the Silicon Valley of Asia – our Aveda Meta campus hosts a world-class team driving next-generation ASIC and SoC development.

The Principal DFT Engineer role is pivotal in ensuring manufacturable, high-yield chips. You'll own end-to-end DFT architecture for complex digital designs, from scan chains and ATPG to advanced MBIST and compression techniques. This hands-on leadership position demands 10+ years of expertise, delivering tapeouts that achieve superior fault coverage while optimizing power, performance, and area (PPA). Join us to shape silicon that powers tomorrow's technologies.

Bangalore's vibrant tech ecosystem, combined with Analog Devices' cutting-edge facilities, creates an unmatched environment for DFT professionals. Collaborate with cross-functional teams on multi-billion-gate SoCs targeting automotive, industrial, and communications markets.

A Day in the Life of a Principal DFT Engineer in Bangalore

Your morning begins with reviewing overnight ATPG runs on our high-performance compute farm. Diving into coverage reports, you identify gaps in transition fault patterns and tweak compression hierarchies for 99%+ coverage. By 10 AM, you're in sync with the RTL team, resolving scan reordering conflicts that impact timing closure.

Lunch at the Aveda Meta cafeteria fuels discussions on 3nm node challenges. Post-lunch, hands-on lab time: debugging a logic BIST failure using JTAG probes and oscilloscopes. Afternoon brings architecture reviews – presenting DFT plans for a 5nm automotive SoC with ISO 26262 safety requirements. You script Python automations to streamline MBIST insertion across IP blocks.

Evenings wrap with mentoring sessions, guiding junior engineers on Tessent flows, followed by collaboration with Singapore ATE teams on pattern optimization. With 10% travel, occasional trips to Wilmington HQ or customer sites keep you connected globally. This dynamic rhythm blends deep technical execution with strategic influence.

Why Bangalore, India for Your DFT Career?

Bangalore, Karnataka's tech capital, pulses with innovation. Home to 8,000+ startups and giants like Infosys, Wipro, and now Analog Devices' expanded campus, it offers unparalleled opportunities. The city's 1,500+ R&D centers drive India's $250B IT industry, with VLSI design at its core.

Aveda Meta's state-of-the-art labs feature advanced emulation farms, silicon validation suites, and high-speed ATE. Beyond work, Bangalore blends gardens, cafes, and Cubbon Park escapes with Nandi Hills adventures. Proximity to Kempegowda Airport facilitates global travel, while a cosmopolitan culture welcomes diverse talents.

India's growing semiconductor push – $10B government incentives – positions Bangalore as Asia's chip design hub. At Analog Devices, you'll thrive amid this momentum, with lower living costs than Silicon Valley yet world-class infrastructure.

Career Growth as Principal DFT Engineer

Analog Devices invests heavily in talent trajectories. As Principal DFT Engineer, you'll lead projects impacting billion-dollar products, fast-tracking to Distinguished Architect or Director roles. Our Individual Contributor track rewards technical excellence with Fellow status.

Access 5,000+ hours of annual training via ADI University – from 3D-IC DFT to AI-driven ATPG. Publish at DAC/ITC, present internally, and rotate across global sites. 90% internal promotion rate reflects our commitment; many Bangalore leaders started as engineers.

Mentorship programs pair you with VP-level sponsors. Equity growth mirrors company success – ADI stock up 200% in 5 years. Certifications in UVM, Tessent, or safety standards are fully funded.

Rewards and Compensation Excellence

Competitive packages include base salaries reflecting 10+ years expertise, annual bonuses (20-30%), and RSUs vesting over 4 years. Full medical, dental, vision for family, plus life/disability coverage. 25+ PTO days, flexible hours, and hybrid options post-ramp.

Wellness stipends, gym memberships, and annual health checks promote balance. Relocation support eases Bangalore transition. Performance ties to stock grants – share in $9B+ revenue growth. Global mobility programs offer US/Europe rotations.

Thriving in Analog Devices' Inclusive Culture

ADI's Ahead of What's Possible ethos fosters collaboration, innovation, and respect. Bangalore's 1,000+ employee team spans 20 nationalities, with ERGs for women, LGBTQ+, and veterans. Hybrid events blend cricket matches, Diwali celebrations, and hackathons.

Leaders embody servant leadership; feedback is continuous via biweekly 1:1s. Innovation hours let you prototype next-gen DFT like ML-based fault prediction. Our equal opportunity commitment ensures merit-based advancement, regardless of background.

Apply Now: Principal DFT Engineer Position

Ready to own DFT for world-changing silicon? Submit your resume highlighting tapeouts, tools, and coverage achievements. Selected candidates enjoy technical interviews with silicon debug scenarios, followed by team fit discussions. Bangalore offers visa support for exceptional global talent.

Join 24,000 innovators ensuring testability powers progress. Apply today – shape the future at Analog Devices.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

Estimated Salary Rangehigh confidence

120,000 - 200,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • DFT architecture and implementationintermediate
  • Scan insertion and ATPGintermediate
  • Boundary scan and JTAGintermediate
  • MBIST and Logic BISTintermediate
  • Test compression techniquesintermediate
  • EDA tools: Synopsys DFT Compilerintermediate
  • Tessent and Cadence Modusintermediate
  • Fault simulation and coverage analysisintermediate
  • TCL/Python/Perl scriptingintermediate
  • RTL design integrationintermediate
  • Timing and synthesis constraintsintermediate
  • Silicon debug and failure analysisintermediate
  • ATE test pattern developmentintermediate
  • Advanced nodes ≤7nm experienceintermediate
  • 2.5D/3D packaging DFTintermediate
  • ISO 26262 safety standardsintermediate
  • Memory BIST for SRAM/DRAMintermediate
  • Production test optimizationintermediate
  • DFT automation flowsintermediate
  • Mentoring and technical documentationintermediate
  • SoC testability methodologiesintermediate
  • High-speed IP testingintermediate
  • Test cost reduction strategiesintermediate
  • Emulation and lab debuggingintermediate

Required Qualifications

  • Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering (experience)
  • 10+ years hands-on DFT experience in ASIC/SoC (experience)
  • Multiple tapeouts for large-scale designs (experience)
  • Expert in scan, ATPG, MBIST, BIST flows (experience)
  • Proficient with Synopsys DFT Compiler, Tessent (experience)
  • Strong EDA tool command including Cadence Modus (experience)
  • Scripting expertise in TCL, Python, Perl (experience)
  • Deep knowledge of RTL, synthesis, timing (experience)
  • Proven silicon debug at lab/production levels (experience)
  • Experience creating technical documentation (experience)
  • Mentoring junior DFT engineers (experience)
  • Advanced nodes (≤7nm) development (experience)
  • 2.5D/3D packaging test strategies (experience)
  • ATE pattern development and analysis (experience)
  • ISO 26262 safety-oriented DFT (experience)
  • Custom macro and memory testing (experience)

Responsibilities

  • Architect and implement DFT for complex ASICs/SoCs
  • Drive scan insertion, ATPG, boundary scan execution
  • Develop MBIST, Logic BIST, JTAG solutions
  • Hands-on EDA tool usage for test generation
  • Validate test plans for stuck-at/transition faults
  • Integrate DFT with RTL and physical design teams
  • Optimize test modes for PPA and yield
  • Debug silicon failures from bring-up to production
  • Implement low-overhead test structures
  • Develop warranty schemes for IP blocks
  • Lab debugging with standard test equipment
  • Document DFT architectures and strategies
  • Create implementation scripts (TCL/Python/Perl)
  • Collaborate with ATE test engineers
  • Reduce test costs and improve coverage
  • Mentor team on DFT best practices
  • Ensure manufacturability and testability

Benefits

  • general: Competitive base salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plans with company match
  • general: Stock purchase and equity grants
  • general: Paid time off and flexible holidays
  • general: Professional development tuition reimbursement
  • general: On-site fitness centers and wellness programs
  • general: Employee stock ownership opportunities
  • general: Relocation assistance for new hires
  • general: Hybrid work flexibility where applicable
  • general: Mental health and counseling services
  • general: Parental leave and family support
  • general: Global mobility and international opportunities
  • general: Learning platforms and certification funding
  • general: Volunteer time off and community programs
  • general: Comprehensive life and disability insurance
  • general: Annual health check-ups and wellness stipends

Target Your Resume for "Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

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Tags & Categories

Principal DFT EngineerAnalog Devices careersDFT jobs BangaloreASIC DFT engineerSoC testability IndiaScan insertion jobsATPG expertMBIST implementationSynopsys Tessent BangaloreCadence Modus rolesSilicon debug engineerVLSI DFT careersSemiconductor jobs IndiaJTAG boundary scanTest compression specialistAdvanced node DFTISO 26262 DFTATE test engineerPython TCL DFT scriptingAnalog Devices BangaloreAveda Meta jobsPrincipal engineer salaryDFT architecture leadEngineeringSemiconductorVLSIDFTASICSoCHardware

Answer 10 quick questions to check your fit for Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now @ Analog Devices.

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Analog Devices logo

Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Principal DFT Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading DFT Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and seamless connectivity. In Bangalore, India – the Silicon Valley of Asia – our Aveda Meta campus hosts a world-class team driving next-generation ASIC and SoC development.

The Principal DFT Engineer role is pivotal in ensuring manufacturable, high-yield chips. You'll own end-to-end DFT architecture for complex digital designs, from scan chains and ATPG to advanced MBIST and compression techniques. This hands-on leadership position demands 10+ years of expertise, delivering tapeouts that achieve superior fault coverage while optimizing power, performance, and area (PPA). Join us to shape silicon that powers tomorrow's technologies.

Bangalore's vibrant tech ecosystem, combined with Analog Devices' cutting-edge facilities, creates an unmatched environment for DFT professionals. Collaborate with cross-functional teams on multi-billion-gate SoCs targeting automotive, industrial, and communications markets.

A Day in the Life of a Principal DFT Engineer in Bangalore

Your morning begins with reviewing overnight ATPG runs on our high-performance compute farm. Diving into coverage reports, you identify gaps in transition fault patterns and tweak compression hierarchies for 99%+ coverage. By 10 AM, you're in sync with the RTL team, resolving scan reordering conflicts that impact timing closure.

Lunch at the Aveda Meta cafeteria fuels discussions on 3nm node challenges. Post-lunch, hands-on lab time: debugging a logic BIST failure using JTAG probes and oscilloscopes. Afternoon brings architecture reviews – presenting DFT plans for a 5nm automotive SoC with ISO 26262 safety requirements. You script Python automations to streamline MBIST insertion across IP blocks.

Evenings wrap with mentoring sessions, guiding junior engineers on Tessent flows, followed by collaboration with Singapore ATE teams on pattern optimization. With 10% travel, occasional trips to Wilmington HQ or customer sites keep you connected globally. This dynamic rhythm blends deep technical execution with strategic influence.

Why Bangalore, India for Your DFT Career?

Bangalore, Karnataka's tech capital, pulses with innovation. Home to 8,000+ startups and giants like Infosys, Wipro, and now Analog Devices' expanded campus, it offers unparalleled opportunities. The city's 1,500+ R&D centers drive India's $250B IT industry, with VLSI design at its core.

Aveda Meta's state-of-the-art labs feature advanced emulation farms, silicon validation suites, and high-speed ATE. Beyond work, Bangalore blends gardens, cafes, and Cubbon Park escapes with Nandi Hills adventures. Proximity to Kempegowda Airport facilitates global travel, while a cosmopolitan culture welcomes diverse talents.

India's growing semiconductor push – $10B government incentives – positions Bangalore as Asia's chip design hub. At Analog Devices, you'll thrive amid this momentum, with lower living costs than Silicon Valley yet world-class infrastructure.

Career Growth as Principal DFT Engineer

Analog Devices invests heavily in talent trajectories. As Principal DFT Engineer, you'll lead projects impacting billion-dollar products, fast-tracking to Distinguished Architect or Director roles. Our Individual Contributor track rewards technical excellence with Fellow status.

Access 5,000+ hours of annual training via ADI University – from 3D-IC DFT to AI-driven ATPG. Publish at DAC/ITC, present internally, and rotate across global sites. 90% internal promotion rate reflects our commitment; many Bangalore leaders started as engineers.

Mentorship programs pair you with VP-level sponsors. Equity growth mirrors company success – ADI stock up 200% in 5 years. Certifications in UVM, Tessent, or safety standards are fully funded.

Rewards and Compensation Excellence

Competitive packages include base salaries reflecting 10+ years expertise, annual bonuses (20-30%), and RSUs vesting over 4 years. Full medical, dental, vision for family, plus life/disability coverage. 25+ PTO days, flexible hours, and hybrid options post-ramp.

Wellness stipends, gym memberships, and annual health checks promote balance. Relocation support eases Bangalore transition. Performance ties to stock grants – share in $9B+ revenue growth. Global mobility programs offer US/Europe rotations.

Thriving in Analog Devices' Inclusive Culture

ADI's Ahead of What's Possible ethos fosters collaboration, innovation, and respect. Bangalore's 1,000+ employee team spans 20 nationalities, with ERGs for women, LGBTQ+, and veterans. Hybrid events blend cricket matches, Diwali celebrations, and hackathons.

Leaders embody servant leadership; feedback is continuous via biweekly 1:1s. Innovation hours let you prototype next-gen DFT like ML-based fault prediction. Our equal opportunity commitment ensures merit-based advancement, regardless of background.

Apply Now: Principal DFT Engineer Position

Ready to own DFT for world-changing silicon? Submit your resume highlighting tapeouts, tools, and coverage achievements. Selected candidates enjoy technical interviews with silicon debug scenarios, followed by team fit discussions. Bangalore offers visa support for exceptional global talent.

Join 24,000 innovators ensuring testability powers progress. Apply today – shape the future at Analog Devices.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

Estimated Salary Rangehigh confidence

120,000 - 200,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • DFT architecture and implementationintermediate
  • Scan insertion and ATPGintermediate
  • Boundary scan and JTAGintermediate
  • MBIST and Logic BISTintermediate
  • Test compression techniquesintermediate
  • EDA tools: Synopsys DFT Compilerintermediate
  • Tessent and Cadence Modusintermediate
  • Fault simulation and coverage analysisintermediate
  • TCL/Python/Perl scriptingintermediate
  • RTL design integrationintermediate
  • Timing and synthesis constraintsintermediate
  • Silicon debug and failure analysisintermediate
  • ATE test pattern developmentintermediate
  • Advanced nodes ≤7nm experienceintermediate
  • 2.5D/3D packaging DFTintermediate
  • ISO 26262 safety standardsintermediate
  • Memory BIST for SRAM/DRAMintermediate
  • Production test optimizationintermediate
  • DFT automation flowsintermediate
  • Mentoring and technical documentationintermediate
  • SoC testability methodologiesintermediate
  • High-speed IP testingintermediate
  • Test cost reduction strategiesintermediate
  • Emulation and lab debuggingintermediate

Required Qualifications

  • Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering (experience)
  • 10+ years hands-on DFT experience in ASIC/SoC (experience)
  • Multiple tapeouts for large-scale designs (experience)
  • Expert in scan, ATPG, MBIST, BIST flows (experience)
  • Proficient with Synopsys DFT Compiler, Tessent (experience)
  • Strong EDA tool command including Cadence Modus (experience)
  • Scripting expertise in TCL, Python, Perl (experience)
  • Deep knowledge of RTL, synthesis, timing (experience)
  • Proven silicon debug at lab/production levels (experience)
  • Experience creating technical documentation (experience)
  • Mentoring junior DFT engineers (experience)
  • Advanced nodes (≤7nm) development (experience)
  • 2.5D/3D packaging test strategies (experience)
  • ATE pattern development and analysis (experience)
  • ISO 26262 safety-oriented DFT (experience)
  • Custom macro and memory testing (experience)

Responsibilities

  • Architect and implement DFT for complex ASICs/SoCs
  • Drive scan insertion, ATPG, boundary scan execution
  • Develop MBIST, Logic BIST, JTAG solutions
  • Hands-on EDA tool usage for test generation
  • Validate test plans for stuck-at/transition faults
  • Integrate DFT with RTL and physical design teams
  • Optimize test modes for PPA and yield
  • Debug silicon failures from bring-up to production
  • Implement low-overhead test structures
  • Develop warranty schemes for IP blocks
  • Lab debugging with standard test equipment
  • Document DFT architectures and strategies
  • Create implementation scripts (TCL/Python/Perl)
  • Collaborate with ATE test engineers
  • Reduce test costs and improve coverage
  • Mentor team on DFT best practices
  • Ensure manufacturability and testability

Benefits

  • general: Competitive base salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plans with company match
  • general: Stock purchase and equity grants
  • general: Paid time off and flexible holidays
  • general: Professional development tuition reimbursement
  • general: On-site fitness centers and wellness programs
  • general: Employee stock ownership opportunities
  • general: Relocation assistance for new hires
  • general: Hybrid work flexibility where applicable
  • general: Mental health and counseling services
  • general: Parental leave and family support
  • general: Global mobility and international opportunities
  • general: Learning platforms and certification funding
  • general: Volunteer time off and community programs
  • general: Comprehensive life and disability insurance
  • general: Annual health check-ups and wellness stipends

Target Your Resume for "Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Get personalized recommendations to optimize your resume specifically for Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Principal DFT EngineerAnalog Devices careersDFT jobs BangaloreASIC DFT engineerSoC testability IndiaScan insertion jobsATPG expertMBIST implementationSynopsys Tessent BangaloreCadence Modus rolesSilicon debug engineerVLSI DFT careersSemiconductor jobs IndiaJTAG boundary scanTest compression specialistAdvanced node DFTISO 26262 DFTATE test engineerPython TCL DFT scriptingAnalog Devices BangaloreAveda Meta jobsPrincipal engineer salaryDFT architecture leadEngineeringSemiconductorVLSIDFTASICSoCHardware

Answer 10 quick questions to check your fit for Principal DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now @ Analog Devices.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.