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Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading Physical Design Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and connectivity. Our Bangalore, India campus in the vibrant Aveda Meta district represents our commitment to Asia-Pacific excellence, hosting cutting-edge R&D for advanced node ICs.

As a Principal Physical Design Engineer, you'll own the end-to-end physical implementation of sophisticated digital ICs—from netlist to GDSII—optimizing for power, performance, and area (PPA) while ensuring flawless signoff. This hands-on role emphasizes technical mastery over management, targeting complex ASICs/SoCs on advanced nodes (≤7nm). Join a team driving tapeouts for next-gen products in Bangalore's thriving tech ecosystem.

Bangalore, often called India's Silicon Valley, offers unparalleled opportunities. Home to 12 million people, it's a hub for semiconductors with world-class infrastructure. Analog Devices' state-of-the-art facility provides the latest EDA tools, high-performance compute farms, and collaborative spaces. Expect 10% travel for cross-site collaborations, primarily 1st shift with hybrid flexibility.

A Day in the Life of a Principal Physical Design Engineer in Bangalore

Your morning begins at 9 AM in our modern Aveda Meta campus, grabbing filter coffee while reviewing overnight STA runs. Dive into floorplanning a 5nm block, using Cadence Innovus to optimize macro placement and power grid density. By 11 AM, collaborate with the RTL team via Slack and stand-ups, refining timing constraints for multi-corner multi-mode (MCMM) analysis.

Lunch features South Indian dosas in the subsidized cafeteria, networking with peers from DFT and synthesis. Post-lunch, tackle clock tree synthesis (CTS) convergence, scripting Python automations to iterate convergence metrics. Afternoons involve IR-drop debugging with RedHawk, followed by DRC/LVS deck reviews. End with peer design reviews, proposing flow enhancements, and wrapping by 6 PM—often with team cricket or table tennis.

This rhythm blends deep technical execution with cross-functional synergy, all amidst Bangalore's pleasant weather and vibrant culture. Weekends? Explore Cubbon Park or Nandi Hills, recharging for Monday's tapeout pushes.

Why Bangalore, India for Your Physical Design Career?

Bangalore, Karnataka's capital, pulses with innovation. As India's third-largest city, it hosts giants like Intel, Texas Instruments, and Qualcomm alongside startups. The Electronic City and Whitefield clusters foster a semiconductor renaissance, with government initiatives like the India Semiconductor Mission investing billions.

Aveda Meta's strategic location offers seamless connectivity via metro and airport proximity. Cost of living remains attractive—luxury apartments at fraction of California prices—while quality soars: international schools, malls like Orion, and healthcare at Apollo Hospitals. Tech events like VLSI Conference and Bangalore Tech Summit keep you connected.

Analog Devices leverages Bangalore's 10 million+ engineering talent pool, building diverse teams fluent in global collaboration. Enjoy monsoon greenery, Diwali festivities, and proximity to Mysore Palace—perfect work-life harmony for ambitious engineers.

Career Growth and Technical Leadership

At Analog Devices, Principals evolve into Distinguished Architects or Directors. Our Individual Contributor track rewards tapeout success with promotions every 2-3 years. Access mentorship from 20+ year veterans, internal universities, and certifications in Synopsys/Cadence tools.

Lead methodology pods, publish at DAC/ITC, and patent innovations. Global rotations to Massachusetts or Limerick expose you to mixed-signal frontiers. With 24,000 employees, upward mobility spans design, CAD, and product engineering. Bangalore's team has produced 50+ tapeouts in 5 years—your contributions will shine.

Rewards and Compensation Excellence

Earn $120K-$200K USD equivalent (₹1Cr+ total comp) with bonuses up to 20%, RSUs, and ESOPs. Benefits include gold-standard health coverage, 25+ PTO days, gym subsidies, and cab services. Relocation packages cover housing for 3 months. Performance ties to tapeout metrics ensure meritocracy.

Thriving Culture at Analog Devices Bangalore

Our inclusive culture celebrates Diwali, Christmas, and Ugadi with team events. Hybrid model balances focus and collaboration; women@ADI initiatives boost diversity (35% female engineers). Innovation Labs host hackathons; CSR drives education in Karnataka villages. LinkedIn Glassdoor rates us 4.5/5 for work-life balance.

Apply Now: Shape the Future of Semiconductors

Ready to tapeout world-class ICs? Submit your resume highlighting tapeouts and tools. U.S. export compliance may apply for non-citizens. EOE committed to diversity.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

120,000 - 200,000 USD / yearly

Estimated Salary Rangehigh confidence

120,000 - 200,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Digital Physical Design Flow Expertiseintermediate
  • Floorplanning and Placement Optimizationintermediate
  • Clock Tree Synthesis (CTS)intermediate
  • Routing and Timing Closureintermediate
  • Static Timing Analysis (STA)intermediate
  • Power Integrity and IR-Drop Analysisintermediate
  • Electromigration (EM) Verificationintermediate
  • Low-Power Design with UPF/CPFintermediate
  • Physical Verification (DRC, LVS, ERC)intermediate
  • EDA Tools: Cadence Innovus, Synopsys ICC2intermediate
  • Mentor Olympus-SoCintermediate
  • TCL and Python Scriptingintermediate
  • Hierarchical Design Partitioningintermediate
  • Advanced Node Implementation (≤7nm)intermediate
  • Hard Macro Integrationintermediate
  • Power Grid and Pad Ring Designintermediate
  • ECO Implementation and Debugintermediate
  • DFT Physical Integrationintermediate
  • Signal Integrity Analysisintermediate
  • CAD Flow Automationintermediate
  • Multi-Voltage Domain Designintermediate
  • Chip Assembly and Signoffintermediate
  • Manufacturability Checksintermediate
  • Antenna Rule Complianceintermediate
  • Reliability Verificationintermediate

Required Qualifications

  • Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering (experience)
  • 10+ years hands-on digital physical design experience (experience)
  • Expertise in ASIC/SoC physical implementation (experience)
  • Advanced FinFET node experience (≤7nm preferred) (experience)
  • Proficiency in Cadence Innovus and Synopsys ICC2 (experience)
  • Mentor Olympus physical design tools (experience)
  • Static Timing Analysis (STA) mastery (experience)
  • Power, Performance, Area (PPA) optimization (experience)
  • IR-drop and EM analysis expertise (experience)
  • Low-power UPF/CPF implementation (experience)
  • Physical verification: DRC, LVS, ERC (experience)
  • TCL, Python, Perl scripting for automation (experience)
  • Proven tapeout success (block and full-chip) (experience)
  • Hierarchical and top-level implementation (experience)
  • Mixed-signal/analog block integration (experience)
  • DFT scan chain stitching at physical level (experience)
  • Strong debug and analytical skills (experience)
  • Excellent documentation abilities (experience)
  • Experience with multi-power domain chips (experience)
  • CAD methodology development (experience)

Responsibilities

  • Own physical implementation from netlist to GDSII
  • Execute block-level and top-level floorplanning
  • Perform placement, CTS, and routing
  • Achieve timing closure across all stages
  • Collaborate with RTL and synthesis teams
  • Develop power integrity strategies
  • Conduct IR-drop analysis and EM verification
  • Implement low-power designs using UPF/CPF
  • Execute physical verification (DRC, LVS, ERC)
  • Integrate hard macros, blocks, and IP
  • Design power grid, pad ring, custom routing
  • Automate flows with TCL/Python scripting
  • Perform design partitioning for complex chips
  • Drive chip assembly for hierarchical designs
  • Interface with DFT, SI/PI, package teams
  • Contribute to methodology improvements
  • Evaluate CAD tools and flows
  • Participate in peer reviews
  • Provide hands-on technical guidance
  • Ensure manufacturability and reliability

Benefits

  • general: Competitive base salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plan with company match
  • general: Stock purchase and equity grants
  • general: Paid time off and flexible holidays
  • general: Professional development budget
  • general: Tuition reimbursement for advanced degrees
  • general: On-site fitness center and wellness programs
  • general: Employee stock ownership opportunities
  • general: Relocation assistance for qualified candidates
  • general: Hybrid work flexibility post-onboarding
  • general: Mental health and counseling services
  • general: Generous parental leave policies
  • general: Volunteer time off program
  • general: Global career mobility opportunities
  • general: Technical conference attendance support
  • general: Cutting-edge hardware and software access
  • general: Team-building events and social activities
  • general: Comprehensive life and disability insurance
  • general: Employee assistance programs

Target Your Resume for "Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

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Tags & Categories

Principal Physical Design EngineerAnalog Devices BangalorePhysical Design Jobs IndiaASIC Physical ImplementationCadence Innovus JobsSynopsys ICC2 CareersAdvanced Node 7nm JobsTiming Closure EngineerLow Power UPF DesignIR Drop Analysis BangaloreVLSI Physical DesignSoC FloorplanningClock Tree Synthesis JobsGDSII Tapeout EngineerSemiconductor Jobs BangaloreFinFET Physical DesignSTA PrimeTime CareersDigital IC Design IndiaPPA Optimization JobsPhysical Verification DRC LVSPython TCL Automation VLSIAnalog Devices CareersBangalore VLSI JobsEngineeringSemiconductorsVLSIPhysical DesignASICHardware

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Analog Devices logo

Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading Physical Design Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, we're enabling breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and connectivity. Our Bangalore, India campus in the vibrant Aveda Meta district represents our commitment to Asia-Pacific excellence, hosting cutting-edge R&D for advanced node ICs.

As a Principal Physical Design Engineer, you'll own the end-to-end physical implementation of sophisticated digital ICs—from netlist to GDSII—optimizing for power, performance, and area (PPA) while ensuring flawless signoff. This hands-on role emphasizes technical mastery over management, targeting complex ASICs/SoCs on advanced nodes (≤7nm). Join a team driving tapeouts for next-gen products in Bangalore's thriving tech ecosystem.

Bangalore, often called India's Silicon Valley, offers unparalleled opportunities. Home to 12 million people, it's a hub for semiconductors with world-class infrastructure. Analog Devices' state-of-the-art facility provides the latest EDA tools, high-performance compute farms, and collaborative spaces. Expect 10% travel for cross-site collaborations, primarily 1st shift with hybrid flexibility.

A Day in the Life of a Principal Physical Design Engineer in Bangalore

Your morning begins at 9 AM in our modern Aveda Meta campus, grabbing filter coffee while reviewing overnight STA runs. Dive into floorplanning a 5nm block, using Cadence Innovus to optimize macro placement and power grid density. By 11 AM, collaborate with the RTL team via Slack and stand-ups, refining timing constraints for multi-corner multi-mode (MCMM) analysis.

Lunch features South Indian dosas in the subsidized cafeteria, networking with peers from DFT and synthesis. Post-lunch, tackle clock tree synthesis (CTS) convergence, scripting Python automations to iterate convergence metrics. Afternoons involve IR-drop debugging with RedHawk, followed by DRC/LVS deck reviews. End with peer design reviews, proposing flow enhancements, and wrapping by 6 PM—often with team cricket or table tennis.

This rhythm blends deep technical execution with cross-functional synergy, all amidst Bangalore's pleasant weather and vibrant culture. Weekends? Explore Cubbon Park or Nandi Hills, recharging for Monday's tapeout pushes.

Why Bangalore, India for Your Physical Design Career?

Bangalore, Karnataka's capital, pulses with innovation. As India's third-largest city, it hosts giants like Intel, Texas Instruments, and Qualcomm alongside startups. The Electronic City and Whitefield clusters foster a semiconductor renaissance, with government initiatives like the India Semiconductor Mission investing billions.

Aveda Meta's strategic location offers seamless connectivity via metro and airport proximity. Cost of living remains attractive—luxury apartments at fraction of California prices—while quality soars: international schools, malls like Orion, and healthcare at Apollo Hospitals. Tech events like VLSI Conference and Bangalore Tech Summit keep you connected.

Analog Devices leverages Bangalore's 10 million+ engineering talent pool, building diverse teams fluent in global collaboration. Enjoy monsoon greenery, Diwali festivities, and proximity to Mysore Palace—perfect work-life harmony for ambitious engineers.

Career Growth and Technical Leadership

At Analog Devices, Principals evolve into Distinguished Architects or Directors. Our Individual Contributor track rewards tapeout success with promotions every 2-3 years. Access mentorship from 20+ year veterans, internal universities, and certifications in Synopsys/Cadence tools.

Lead methodology pods, publish at DAC/ITC, and patent innovations. Global rotations to Massachusetts or Limerick expose you to mixed-signal frontiers. With 24,000 employees, upward mobility spans design, CAD, and product engineering. Bangalore's team has produced 50+ tapeouts in 5 years—your contributions will shine.

Rewards and Compensation Excellence

Earn $120K-$200K USD equivalent (₹1Cr+ total comp) with bonuses up to 20%, RSUs, and ESOPs. Benefits include gold-standard health coverage, 25+ PTO days, gym subsidies, and cab services. Relocation packages cover housing for 3 months. Performance ties to tapeout metrics ensure meritocracy.

Thriving Culture at Analog Devices Bangalore

Our inclusive culture celebrates Diwali, Christmas, and Ugadi with team events. Hybrid model balances focus and collaboration; women@ADI initiatives boost diversity (35% female engineers). Innovation Labs host hackathons; CSR drives education in Karnataka villages. LinkedIn Glassdoor rates us 4.5/5 for work-life balance.

Apply Now: Shape the Future of Semiconductors

Ready to tapeout world-class ICs? Submit your resume highlighting tapeouts and tools. U.S. export compliance may apply for non-citizens. EOE committed to diversity.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

120,000 - 200,000 USD / yearly

Estimated Salary Rangehigh confidence

120,000 - 200,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Digital Physical Design Flow Expertiseintermediate
  • Floorplanning and Placement Optimizationintermediate
  • Clock Tree Synthesis (CTS)intermediate
  • Routing and Timing Closureintermediate
  • Static Timing Analysis (STA)intermediate
  • Power Integrity and IR-Drop Analysisintermediate
  • Electromigration (EM) Verificationintermediate
  • Low-Power Design with UPF/CPFintermediate
  • Physical Verification (DRC, LVS, ERC)intermediate
  • EDA Tools: Cadence Innovus, Synopsys ICC2intermediate
  • Mentor Olympus-SoCintermediate
  • TCL and Python Scriptingintermediate
  • Hierarchical Design Partitioningintermediate
  • Advanced Node Implementation (≤7nm)intermediate
  • Hard Macro Integrationintermediate
  • Power Grid and Pad Ring Designintermediate
  • ECO Implementation and Debugintermediate
  • DFT Physical Integrationintermediate
  • Signal Integrity Analysisintermediate
  • CAD Flow Automationintermediate
  • Multi-Voltage Domain Designintermediate
  • Chip Assembly and Signoffintermediate
  • Manufacturability Checksintermediate
  • Antenna Rule Complianceintermediate
  • Reliability Verificationintermediate

Required Qualifications

  • Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering (experience)
  • 10+ years hands-on digital physical design experience (experience)
  • Expertise in ASIC/SoC physical implementation (experience)
  • Advanced FinFET node experience (≤7nm preferred) (experience)
  • Proficiency in Cadence Innovus and Synopsys ICC2 (experience)
  • Mentor Olympus physical design tools (experience)
  • Static Timing Analysis (STA) mastery (experience)
  • Power, Performance, Area (PPA) optimization (experience)
  • IR-drop and EM analysis expertise (experience)
  • Low-power UPF/CPF implementation (experience)
  • Physical verification: DRC, LVS, ERC (experience)
  • TCL, Python, Perl scripting for automation (experience)
  • Proven tapeout success (block and full-chip) (experience)
  • Hierarchical and top-level implementation (experience)
  • Mixed-signal/analog block integration (experience)
  • DFT scan chain stitching at physical level (experience)
  • Strong debug and analytical skills (experience)
  • Excellent documentation abilities (experience)
  • Experience with multi-power domain chips (experience)
  • CAD methodology development (experience)

Responsibilities

  • Own physical implementation from netlist to GDSII
  • Execute block-level and top-level floorplanning
  • Perform placement, CTS, and routing
  • Achieve timing closure across all stages
  • Collaborate with RTL and synthesis teams
  • Develop power integrity strategies
  • Conduct IR-drop analysis and EM verification
  • Implement low-power designs using UPF/CPF
  • Execute physical verification (DRC, LVS, ERC)
  • Integrate hard macros, blocks, and IP
  • Design power grid, pad ring, custom routing
  • Automate flows with TCL/Python scripting
  • Perform design partitioning for complex chips
  • Drive chip assembly for hierarchical designs
  • Interface with DFT, SI/PI, package teams
  • Contribute to methodology improvements
  • Evaluate CAD tools and flows
  • Participate in peer reviews
  • Provide hands-on technical guidance
  • Ensure manufacturability and reliability

Benefits

  • general: Competitive base salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plan with company match
  • general: Stock purchase and equity grants
  • general: Paid time off and flexible holidays
  • general: Professional development budget
  • general: Tuition reimbursement for advanced degrees
  • general: On-site fitness center and wellness programs
  • general: Employee stock ownership opportunities
  • general: Relocation assistance for qualified candidates
  • general: Hybrid work flexibility post-onboarding
  • general: Mental health and counseling services
  • general: Generous parental leave policies
  • general: Volunteer time off program
  • general: Global career mobility opportunities
  • general: Technical conference attendance support
  • general: Cutting-edge hardware and software access
  • general: Team-building events and social activities
  • general: Comprehensive life and disability insurance
  • general: Employee assistance programs

Target Your Resume for "Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Get personalized recommendations to optimize your resume specifically for Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Principal Physical Design EngineerAnalog Devices BangalorePhysical Design Jobs IndiaASIC Physical ImplementationCadence Innovus JobsSynopsys ICC2 CareersAdvanced Node 7nm JobsTiming Closure EngineerLow Power UPF DesignIR Drop Analysis BangaloreVLSI Physical DesignSoC FloorplanningClock Tree Synthesis JobsGDSII Tapeout EngineerSemiconductor Jobs BangaloreFinFET Physical DesignSTA PrimeTime CareersDigital IC Design IndiaPPA Optimization JobsPhysical Verification DRC LVSPython TCL Automation VLSIAnalog Devices CareersBangalore VLSI JobsEngineeringSemiconductorsVLSIPhysical DesignASICHardware

Answer 10 quick questions to check your fit for Principal Physical Design Engineer Careers at Analog Devices in Bangalore, India | Apply Now @ Analog Devices.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.