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Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Senior DFT Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading DFT Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, ADI drives breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and connectivity. Our Bangalore center in Aveda Meta represents a hub of excellence for Design-for-Test (DFT) engineering, where Senior DFT Engineers architect test strategies for cutting-edge SoCs that redefine industry standards.

In this pivotal role, you'll shape DFT architectures that ensure manufacturability, high test coverage, and cost efficiency for complex System-on-Chips. Bangalore's thriving tech ecosystem combined with ADI's world-class resources positions you at the intersection of innovation and execution. From hierarchical scan compression to MBIST implementation and post-silicon validation, your expertise will directly impact products that stay Ahead of What's Possible™.

The Senior DFT Engineer role demands 4-8 years of hands-on experience, proven success bringing products to production, and mastery of industry-leading tools like Tessent. This isn't just a job—it's a career-defining opportunity to influence global semiconductor test methodologies while thriving in India's Silicon Valley.

A Day in the Life of a Senior DFT Engineer in Bangalore

Your morning begins with cross-functional sync-ups via global collaboration tools, reviewing SoC architecture updates from design teams in Massachusetts and Limerick. By 10 AM, you're deep into DFT architecture refinement—partitioning scan chains for optimal compression while balancing at-speed test requirements and low-power constraints.

Mid-morning involves flow development: scripting Perl/Python automations to streamline MBIST insertion across memory IP blocks. Lunch at Aveda Meta's vibrant cafeteria sparks ideas with colleagues from physical design and product engineering. Post-lunch, you tackle ATPG pattern generation, validating multi-corner fault models and debugging timing violations in Cadence Tempus.

Afternoon brings hierarchical scan re-convergence meetings with block owners, ensuring top-level DFT integrity. As patterns mature, you simulate SCAN/MBIST/BSCAN vectors, correlating with gate-level netlists. Evenings often include failure analysis reviews from silicon bring-up or yield optimization discussions with operations teams. Weekly, you mentor junior engineers, sharing post-silicon war stories from ATE bring-ups that shaved test costs by 30%.

This dynamic rhythm blends deep technical dives with strategic influence, all within Bangalore's innovative ecosystem where work-life balance meets world-class challenges.

Why Bangalore, India: India's Silicon Valley Beckons

Bangalore, Karnataka's tech capital, hosts over 1,500 multinational tech firms and produces 40% of India's IT exports. Home to IISc, IIM Bangalore, and a 1.5 million-strong tech workforce, the city offers unmatched talent density and innovation infrastructure. Analog Devices' Aveda Meta campus leverages this ecosystem while providing state-of-the-art labs, high-speed connectivity, and proximity to Electronic City’s semiconductor cluster.

Beyond professional advantages, Bangalore blends cosmopolitan vibrancy with cultural richness. UB City offers global cuisine, while Cubbon Park provides green respite. The metro connects you seamlessly to Kempegowda Airport for 10% travel requirements. With 300+ sunny days annually and a perpetual spring climate, Bangalore supports both career acceleration and personal fulfillment.

ADI's Bangalore investment reflects confidence in India's semiconductor destiny—$10B government incentives, 20 new fabs planned, and a $100B+ market projection by 2030 position you at ground zero for Asia's chip renaissance.

Career Growth: From Senior DFT to DFT Architecture Leadership

Analog Devices invests heavily in technical leadership development. Senior DFT Engineers follow clear paths to Principal Engineer, DFT Architect, and Director roles. 70% of our engineering managers began as individual contributors. Access mentorship from ADI Fellows, global technical ladders, and cross-site rotations to Wilmington, Massachusetts or Graz, Austria.

Annual Individual Development Plans include $5,000 training budgets for DFT conferences (ITC, VTS), Tessent advanced training, and MBIST specialization. Internal mobility spans 50+ global sites. Our Bangalore team has produced 3 DFT Distinguished Members in 5 years, with promotion rates 25% above industry averages.

Rewards: Exceptional Compensation in India's Tech Capital

ADI offers top-quartile total compensation: base salaries 20-30% above Bangalore market, target bonuses 15-25%, and RSUs vesting over 4 years. Comprehensive benefits include family health coverage (no co-pay for hospitalization), 25+ annual leaves, 2 months parental leave, and 8 GPA flex days.

Unique perks feature on-campus medical center, gym with personal trainers, subsidized electric vehicle charging, and annual health checkups. Professional growth includes conference sponsorships, patent bonuses ($5K+ per granted patent), and President's Club awards with Silicon Valley trips. Relocation packages cover housing for 3 months, visa/spousal support, and school admissions assistance.

Culture: Innovation, Inclusion, and Impact at ADI

Analog Devices cultivates a culture of psychological safety where engineers influence tape-outs worth billions. Our 4.3/5 Glassdoor rating reflects transparent leadership, zero-tolerance for politics, and celebration of technical excellence. Bangalore's 500+ person team embodies 'One ADI'—cross-pollinating ideas from RF, power management, and processor teams.

Diversity initiatives yield 35% women in technical roles (2x industry average). ERGs for veterans, LGBTQ+, and women engineers foster belonging. Hackathons, patent workshops, and 'Tech Talks' with ADI CTOs keep innovation flowing. Social impact through ADI Foundation supports 50+ STEM scholarships annually in Karnataka.

Apply Now: Your DFT Career Starts Here

Join 24,000 innovators shaping the future. Successful candidates demonstrate production silicon experience, Tessent mastery, and passion for test innovation. Submit your resume showcasing DFT tape-outs, automation scripts, and yield improvements. Global teams interview via Zoom; Bangalore offers hybrid flexibility post-offer.

ADI is an equal opportunity employer valuing diverse perspectives. U.S. export compliance applies. Selected candidates receive offers within 2 weeks, with start dates flexible around notice periods. Don't miss this chance to architect test strategies for tomorrow's breakthroughs.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

80,000 - 120,000 USD / yearly

Estimated Salary Rangehigh confidence

80,000 - 120,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • DFT Architecture Definitionintermediate
  • Scan Chain Implementationintermediate
  • MBIST for Memoriesintermediate
  • JTAG Boundary Scanintermediate
  • ATPG Pattern Generationintermediate
  • Tessent DFT Toolsintermediate
  • Timing Constraints Developmentintermediate
  • Post-Silicon Validationintermediate
  • Perl Scriptingintermediate
  • Python Automationintermediate
  • TCL Scriptingintermediate
  • HDL Proficiency (Verilog/VHDL)intermediate
  • Low Power DFT (UPF/CPF)intermediate
  • Hierarchical Scan Methodologyintermediate
  • Test Compression (EDT)intermediate
  • Failure Analysisintermediate
  • Yield Optimizationintermediate
  • Cadence Genus/Tempusintermediate
  • Physical Design Integrationintermediate
  • ATE Pattern Bring-upintermediate
  • SoC Test Strategyintermediate
  • Deep Submicron Effectsintermediate
  • Cross-functional Collaborationintermediate

Required Qualifications

  • 4-8 years DFT industry experience (experience)
  • Successful production of 1-2 products from architecture to silicon (experience)
  • Hands-on post-silicon bring-up experience (experience)
  • Tessent DFT tools expertise (SCAN, MBIST, LBIST, OCC, EDT, SSN) (experience)
  • Exceptional communication and collaboration skills (experience)
  • Scripting proficiency in Perl/Python/TCL (experience)
  • Strong HDL command (Verilog/VHDL) (experience)
  • Deep submicron and low power implementation knowledge (experience)
  • Cadence digital implementation tools experience (experience)
  • Timing closure and physical design background (experience)
  • Experience with analog macro testing (experience)
  • Global team collaboration capability (experience)
  • ATE test engineering coordination (experience)
  • Yield improvement methodologies (experience)
  • Hierarchical scan implementation (experience)
  • Test cost optimization expertise (experience)

Responsibilities

  • Define comprehensive DFT architecture for SoCs
  • Optimize scan partition, compression, at-speed testing
  • Implement MBIST for memory arrays
  • Insert JTAG boundary scan structures
  • Develop SCAN and MBIST insertion flows
  • Create timing constraints for test modes
  • Debug and resolve timing violations
  • Implement ATPG flows for multiple fault models
  • Generate and validate test patterns
  • Simulate SCAN, MBIST, and BSCAN patterns
  • Develop solutions for analog macro testing
  • Support post-silicon ATE bring-up
  • Perform failure analysis and debug
  • Collaborate on test cost and yield improvements
  • Guide new team members on DFT methodologies
  • Work closely with physical design teams
  • Stay current with industry DFT best practices

Benefits

  • general: Competitive salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plan with company match
  • general: Paid time off and flexible holidays
  • general: Professional development budget
  • general: Stock purchase plan with discounts
  • general: On-site fitness center and wellness programs
  • general: Employee assistance programs
  • general: Tuition reimbursement for advanced degrees
  • general: Relocation assistance for qualified candidates
  • general: Hybrid work flexibility
  • general: Comprehensive parental leave policies
  • general: Mental health support resources
  • general: Global career mobility opportunities
  • general: Technical conference attendance sponsorship
  • general: Innovation recognition awards
  • general: Team building and social events

Target Your Resume for "Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

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Senior DFT EngineerAnalog Devices careersDFT jobs BangaloreScan chain architectMBIST implementationTessent DFT expertATPG pattern generationPost-silicon validationSoC test strategyHierarchical scanTest compression EDTJTAG boundary scanSemiconductor test engineerBangalore tech jobsIndia semiconductor careersLow power DFT UPFATE bring-up specialistYield optimizationCadence Genus TempusPhysical design DFTPerl Python TCL scriptingAnalog Devices BangaloreEngineeringSemiconductorDFTTest EngineeringHardware DesignSoC Design

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Analog Devices logo

Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

Analog Devices

Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now

full-timePosted: Feb 4, 2026

Job Description

Senior DFT Engineer Careers at Analog Devices in Bangalore, India

Overview: Leading DFT Innovation at Analog Devices Bangalore

Analog Devices stands at the forefront of semiconductor innovation, bridging physical and digital realms to power the Intelligent Edge. With over $9 billion in FY24 revenue and 24,000 global employees, ADI drives breakthroughs in digitized factories, mobility, digital healthcare, climate solutions, and connectivity. Our Bangalore center in Aveda Meta represents a hub of excellence for Design-for-Test (DFT) engineering, where Senior DFT Engineers architect test strategies for cutting-edge SoCs that redefine industry standards.

In this pivotal role, you'll shape DFT architectures that ensure manufacturability, high test coverage, and cost efficiency for complex System-on-Chips. Bangalore's thriving tech ecosystem combined with ADI's world-class resources positions you at the intersection of innovation and execution. From hierarchical scan compression to MBIST implementation and post-silicon validation, your expertise will directly impact products that stay Ahead of What's Possible™.

The Senior DFT Engineer role demands 4-8 years of hands-on experience, proven success bringing products to production, and mastery of industry-leading tools like Tessent. This isn't just a job—it's a career-defining opportunity to influence global semiconductor test methodologies while thriving in India's Silicon Valley.

A Day in the Life of a Senior DFT Engineer in Bangalore

Your morning begins with cross-functional sync-ups via global collaboration tools, reviewing SoC architecture updates from design teams in Massachusetts and Limerick. By 10 AM, you're deep into DFT architecture refinement—partitioning scan chains for optimal compression while balancing at-speed test requirements and low-power constraints.

Mid-morning involves flow development: scripting Perl/Python automations to streamline MBIST insertion across memory IP blocks. Lunch at Aveda Meta's vibrant cafeteria sparks ideas with colleagues from physical design and product engineering. Post-lunch, you tackle ATPG pattern generation, validating multi-corner fault models and debugging timing violations in Cadence Tempus.

Afternoon brings hierarchical scan re-convergence meetings with block owners, ensuring top-level DFT integrity. As patterns mature, you simulate SCAN/MBIST/BSCAN vectors, correlating with gate-level netlists. Evenings often include failure analysis reviews from silicon bring-up or yield optimization discussions with operations teams. Weekly, you mentor junior engineers, sharing post-silicon war stories from ATE bring-ups that shaved test costs by 30%.

This dynamic rhythm blends deep technical dives with strategic influence, all within Bangalore's innovative ecosystem where work-life balance meets world-class challenges.

Why Bangalore, India: India's Silicon Valley Beckons

Bangalore, Karnataka's tech capital, hosts over 1,500 multinational tech firms and produces 40% of India's IT exports. Home to IISc, IIM Bangalore, and a 1.5 million-strong tech workforce, the city offers unmatched talent density and innovation infrastructure. Analog Devices' Aveda Meta campus leverages this ecosystem while providing state-of-the-art labs, high-speed connectivity, and proximity to Electronic City’s semiconductor cluster.

Beyond professional advantages, Bangalore blends cosmopolitan vibrancy with cultural richness. UB City offers global cuisine, while Cubbon Park provides green respite. The metro connects you seamlessly to Kempegowda Airport for 10% travel requirements. With 300+ sunny days annually and a perpetual spring climate, Bangalore supports both career acceleration and personal fulfillment.

ADI's Bangalore investment reflects confidence in India's semiconductor destiny—$10B government incentives, 20 new fabs planned, and a $100B+ market projection by 2030 position you at ground zero for Asia's chip renaissance.

Career Growth: From Senior DFT to DFT Architecture Leadership

Analog Devices invests heavily in technical leadership development. Senior DFT Engineers follow clear paths to Principal Engineer, DFT Architect, and Director roles. 70% of our engineering managers began as individual contributors. Access mentorship from ADI Fellows, global technical ladders, and cross-site rotations to Wilmington, Massachusetts or Graz, Austria.

Annual Individual Development Plans include $5,000 training budgets for DFT conferences (ITC, VTS), Tessent advanced training, and MBIST specialization. Internal mobility spans 50+ global sites. Our Bangalore team has produced 3 DFT Distinguished Members in 5 years, with promotion rates 25% above industry averages.

Rewards: Exceptional Compensation in India's Tech Capital

ADI offers top-quartile total compensation: base salaries 20-30% above Bangalore market, target bonuses 15-25%, and RSUs vesting over 4 years. Comprehensive benefits include family health coverage (no co-pay for hospitalization), 25+ annual leaves, 2 months parental leave, and 8 GPA flex days.

Unique perks feature on-campus medical center, gym with personal trainers, subsidized electric vehicle charging, and annual health checkups. Professional growth includes conference sponsorships, patent bonuses ($5K+ per granted patent), and President's Club awards with Silicon Valley trips. Relocation packages cover housing for 3 months, visa/spousal support, and school admissions assistance.

Culture: Innovation, Inclusion, and Impact at ADI

Analog Devices cultivates a culture of psychological safety where engineers influence tape-outs worth billions. Our 4.3/5 Glassdoor rating reflects transparent leadership, zero-tolerance for politics, and celebration of technical excellence. Bangalore's 500+ person team embodies 'One ADI'—cross-pollinating ideas from RF, power management, and processor teams.

Diversity initiatives yield 35% women in technical roles (2x industry average). ERGs for veterans, LGBTQ+, and women engineers foster belonging. Hackathons, patent workshops, and 'Tech Talks' with ADI CTOs keep innovation flowing. Social impact through ADI Foundation supports 50+ STEM scholarships annually in Karnataka.

Apply Now: Your DFT Career Starts Here

Join 24,000 innovators shaping the future. Successful candidates demonstrate production silicon experience, Tessent mastery, and passion for test innovation. Submit your resume showcasing DFT tape-outs, automation scripts, and yield improvements. Global teams interview via Zoom; Bangalore offers hybrid flexibility post-offer.

ADI is an equal opportunity employer valuing diverse perspectives. U.S. export compliance applies. Selected candidates receive offers within 2 weeks, with start dates flexible around notice periods. Don't miss this chance to architect test strategies for tomorrow's breakthroughs.

Frequently Asked Questions

Locations

  • Bangalore, Karnataka, India

Salary

80,000 - 120,000 USD / yearly

Estimated Salary Rangehigh confidence

80,000 - 120,000 USD / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • DFT Architecture Definitionintermediate
  • Scan Chain Implementationintermediate
  • MBIST for Memoriesintermediate
  • JTAG Boundary Scanintermediate
  • ATPG Pattern Generationintermediate
  • Tessent DFT Toolsintermediate
  • Timing Constraints Developmentintermediate
  • Post-Silicon Validationintermediate
  • Perl Scriptingintermediate
  • Python Automationintermediate
  • TCL Scriptingintermediate
  • HDL Proficiency (Verilog/VHDL)intermediate
  • Low Power DFT (UPF/CPF)intermediate
  • Hierarchical Scan Methodologyintermediate
  • Test Compression (EDT)intermediate
  • Failure Analysisintermediate
  • Yield Optimizationintermediate
  • Cadence Genus/Tempusintermediate
  • Physical Design Integrationintermediate
  • ATE Pattern Bring-upintermediate
  • SoC Test Strategyintermediate
  • Deep Submicron Effectsintermediate
  • Cross-functional Collaborationintermediate

Required Qualifications

  • 4-8 years DFT industry experience (experience)
  • Successful production of 1-2 products from architecture to silicon (experience)
  • Hands-on post-silicon bring-up experience (experience)
  • Tessent DFT tools expertise (SCAN, MBIST, LBIST, OCC, EDT, SSN) (experience)
  • Exceptional communication and collaboration skills (experience)
  • Scripting proficiency in Perl/Python/TCL (experience)
  • Strong HDL command (Verilog/VHDL) (experience)
  • Deep submicron and low power implementation knowledge (experience)
  • Cadence digital implementation tools experience (experience)
  • Timing closure and physical design background (experience)
  • Experience with analog macro testing (experience)
  • Global team collaboration capability (experience)
  • ATE test engineering coordination (experience)
  • Yield improvement methodologies (experience)
  • Hierarchical scan implementation (experience)
  • Test cost optimization expertise (experience)

Responsibilities

  • Define comprehensive DFT architecture for SoCs
  • Optimize scan partition, compression, at-speed testing
  • Implement MBIST for memory arrays
  • Insert JTAG boundary scan structures
  • Develop SCAN and MBIST insertion flows
  • Create timing constraints for test modes
  • Debug and resolve timing violations
  • Implement ATPG flows for multiple fault models
  • Generate and validate test patterns
  • Simulate SCAN, MBIST, and BSCAN patterns
  • Develop solutions for analog macro testing
  • Support post-silicon ATE bring-up
  • Perform failure analysis and debug
  • Collaborate on test cost and yield improvements
  • Guide new team members on DFT methodologies
  • Work closely with physical design teams
  • Stay current with industry DFT best practices

Benefits

  • general: Competitive salary with performance bonuses
  • general: Comprehensive health insurance coverage
  • general: Retirement savings plan with company match
  • general: Paid time off and flexible holidays
  • general: Professional development budget
  • general: Stock purchase plan with discounts
  • general: On-site fitness center and wellness programs
  • general: Employee assistance programs
  • general: Tuition reimbursement for advanced degrees
  • general: Relocation assistance for qualified candidates
  • general: Hybrid work flexibility
  • general: Comprehensive parental leave policies
  • general: Mental health support resources
  • general: Global career mobility opportunities
  • general: Technical conference attendance sponsorship
  • general: Innovation recognition awards
  • general: Team building and social events

Target Your Resume for "Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Get personalized recommendations to optimize your resume specifically for Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now" , Analog Devices

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Senior DFT EngineerAnalog Devices careersDFT jobs BangaloreScan chain architectMBIST implementationTessent DFT expertATPG pattern generationPost-silicon validationSoC test strategyHierarchical scanTest compression EDTJTAG boundary scanSemiconductor test engineerBangalore tech jobsIndia semiconductor careersLow power DFT UPFATE bring-up specialistYield optimizationCadence Genus TempusPhysical design DFTPerl Python TCL scriptingAnalog Devices BangaloreEngineeringSemiconductorDFTTest EngineeringHardware DesignSoC Design

Answer 10 quick questions to check your fit for Senior DFT Engineer Careers at Analog Devices in Bangalore, India | Apply Now @ Analog Devices.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.