AMS SerDes Robustness Analysis & Validation Architect
Apple
AMS SerDes Robustness Analysis & Validation Architect
Job Description
Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques! You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires strong collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production and to ensure the IP is designed with design for testability. - Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments - Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc. - Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc. - Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions - Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints - Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates - Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology - Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analytical skillsintermediate
- hands-on approachintermediate
- SerDes design principlesintermediate
- SerDes validation principlesintermediate
- SOC/system integrationintermediate
- real-world system environmentsintermediate
- stress testingintermediate
- margin-finding techniquesintermediate
- validation strategiesintermediate
- stress-to-fail methodologiesintermediate
- equalization pathsintermediate
- clocking structuresintermediate
- jitter sensitivitiesintermediate
- link trainingintermediate
- design-for-test (DFT)intermediate
- observability techniquesintermediate
- pattern generatorsintermediate
- lab experimentsintermediate
- root-cause analysisintermediate
- test coverage optimizationintermediate
- silicon behavior analysisintermediate
- debug techniquesintermediate
- collaboration skillsintermediate
- leadership skillsintermediate
- guiding junior engineersintermediate
Required Qualifications
- BS and a minimum of 20 years relevant industry experience or equivalent (experience, 20 years)
- 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug (experience, 10 years)
Preferred Qualifications
- PhD in Electrical Engineering or related field with 15+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug (experience, 15 years)
- Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and (experience)
- measurement setups tailored for SerDes PHYs (experience)
- Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE etc) (experience)
- Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts (experience)
- Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies (experience)
- Proven track record to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels (experience)
- Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks (experience)
- Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems (experience)
- Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques (experience)
- Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage (experience)
- Experience providing post-silicon insights that shaped future design changes (experience)
- Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected (experience)
Responsibilities
- - Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments
- - Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc.
- - Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc.
- - Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions
- - Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints
- - Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates
- - Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology
- - Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Tags & Categories
Answer 10 quick questions to check your fit for AMS SerDes Robustness Analysis & Validation Architect @ Apple.
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AMS SerDes Robustness Analysis & Validation Architect
Apple
AMS SerDes Robustness Analysis & Validation Architect
Job Description
Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques! You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires strong collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production and to ensure the IP is designed with design for testability. - Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments - Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc. - Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc. - Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions - Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints - Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates - Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology - Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analytical skillsintermediate
- hands-on approachintermediate
- SerDes design principlesintermediate
- SerDes validation principlesintermediate
- SOC/system integrationintermediate
- real-world system environmentsintermediate
- stress testingintermediate
- margin-finding techniquesintermediate
- validation strategiesintermediate
- stress-to-fail methodologiesintermediate
- equalization pathsintermediate
- clocking structuresintermediate
- jitter sensitivitiesintermediate
- link trainingintermediate
- design-for-test (DFT)intermediate
- observability techniquesintermediate
- pattern generatorsintermediate
- lab experimentsintermediate
- root-cause analysisintermediate
- test coverage optimizationintermediate
- silicon behavior analysisintermediate
- debug techniquesintermediate
- collaboration skillsintermediate
- leadership skillsintermediate
- guiding junior engineersintermediate
Required Qualifications
- BS and a minimum of 20 years relevant industry experience or equivalent (experience, 20 years)
- 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug (experience, 10 years)
Preferred Qualifications
- PhD in Electrical Engineering or related field with 15+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug (experience, 15 years)
- Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and (experience)
- measurement setups tailored for SerDes PHYs (experience)
- Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE etc) (experience)
- Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts (experience)
- Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies (experience)
- Proven track record to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels (experience)
- Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks (experience)
- Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems (experience)
- Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques (experience)
- Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage (experience)
- Experience providing post-silicon insights that shaped future design changes (experience)
- Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected (experience)
Responsibilities
- - Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments
- - Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc.
- - Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc.
- - Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions
- - Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints
- - Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates
- - Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology
- - Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Tags & Categories
Answer 10 quick questions to check your fit for AMS SerDes Robustness Analysis & Validation Architect @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs