Analog IP Layout Lead - Advanced Technologies Group
Apple
Analog IP Layout Lead - Advanced Technologies Group
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP layout lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production. Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following: Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies. Reviewing and analyzing floor-plans and complex circuits with circuit designers. Running complete set of design verification tools available on AMS blocks. Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
Locations
- Haifa, Haifa District, Israel 31905
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analog layout designintermediate
- mixed-signal IP developmentintermediate
- physical design verificationintermediate
- crafting complex layout for mixed-signal and analog circuitsintermediate
- deep submicron CMOS technologiesintermediate
- reviewing and analyzing floor-plansintermediate
- analyzing complex circuitsintermediate
- running design verification toolsintermediate
- collaborating with circuit design teamsintermediate
- planning and scheduling workintermediate
- negotiating layout trade-offsintermediate
- interpreting LVS reportsintermediate
- interpreting DRC reportsintermediate
- interpreting ERC reportsintermediate
- utilizing advanced CAD toolsintermediate
- mask design knowledgeintermediate
- meeting matching performance requirementsintermediate
- meeting area requirementsintermediate
- meeting power requirementsintermediate
Responsibilities
- Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
- As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
- Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
- Reviewing and analyzing floor-plans and complex circuits with circuit designers.
- Running complete set of design verification tools available on AMS blocks.
- Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
- Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
- Exceeding engineering specifications and expectations by working closely with the circuit design team.
- Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
Tags & Categories
Analog IP Layout Lead - Advanced Technologies Group
Apple
Analog IP Layout Lead - Advanced Technologies Group
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP layout lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production. Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following: Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies. Reviewing and analyzing floor-plans and complex circuits with circuit designers. Running complete set of design verification tools available on AMS blocks. Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
Locations
- Haifa, Haifa District, Israel 31905
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analog layout designintermediate
- mixed-signal IP developmentintermediate
- physical design verificationintermediate
- crafting complex layout for mixed-signal and analog circuitsintermediate
- deep submicron CMOS technologiesintermediate
- reviewing and analyzing floor-plansintermediate
- analyzing complex circuitsintermediate
- running design verification toolsintermediate
- collaborating with circuit design teamsintermediate
- planning and scheduling workintermediate
- negotiating layout trade-offsintermediate
- interpreting LVS reportsintermediate
- interpreting DRC reportsintermediate
- interpreting ERC reportsintermediate
- utilizing advanced CAD toolsintermediate
- mask design knowledgeintermediate
- meeting matching performance requirementsintermediate
- meeting area requirementsintermediate
- meeting power requirementsintermediate
Responsibilities
- Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
- As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
- Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
- Reviewing and analyzing floor-plans and complex circuits with circuit designers.
- Running complete set of design verification tools available on AMS blocks.
- Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
- Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
- Exceeding engineering specifications and expectations by working closely with the circuit design team.
- Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
Tags & Categories