Job Description

Locations

• Irvine, California, United States 92602
• San Diego, California, United States 92128
• Sunnyvale, California, United States 94085

Salary

Skills Required

• SoC power estimationintermediate
• power analysisintermediate
• power optimizationintermediate
• power simulationintermediate
• developing power-efficient SoCsintermediate
• define power-critical use casesintermediate
• establish power targetsintermediate
• collaborate with cross-functional teamsintermediate
• define comprehensive test casesintermediate
• design verificationintermediate
• generate pre-silicon power estimationsintermediate
• analyze power consumption patternsintermediate
• identify optimization opportunitiesintermediate
• develop SoC power modelsintermediate
• performance/power trade-off analysisintermediate
• understand software and system-level interactionsintermediate
• partner with lab and silicon characterization teamsintermediate
• correlate models with measured silicon dataintermediate

Required Qualifications

• BS in Electrical Engineering, Computer Engineering, or related technical field and 10+ years of relevant industry experience. (experience, 10 years)
• Hands-on experience with PtPx and PPRTL power analysis tools. (experience)
• Experience in SoC power simulation, modeling, and analysis flow development. (experience)
• Experience in ASIC power estimation, analysis and optimization methodologies. (experience)
• Experience in power model development for IPs. (experience)
• Hands-on experience in correlating pre-silicon power models with measured silicon data and driving model accuracy improvements through systematic debugging. (experience)
• Proficiency in scripting languages including Python, Perl, or TCL. (experience)

Preferred Qualifications

• Understanding of electrical properties of on-die PDN, power gating, package and system power delivery. (experience)
• Hands-on experience with SoC power domains and power management unit (PMU) interactions in complex multi-core chipsets. (experience)
• Knowledge of power impact at architecture, logic design, and circuit levels. (experience)
• Experience in power model development for complex SoCs. (experience)
• Familiarity with SoC design flow and methodology. (experience)
• Strong communication skills to collaborate effectively across multiple engineering disciplines. (experience)
• Knowledge of WiFi or Bluetooth standards and protocols. (experience)

Responsibilities

• In this highly visible role, you will be responsible for SoC power estimation, use case power analysis, and driving future SoC power optimization strategies. You will work with a team of talented engineers to integrate innovative power solutions and deliver industry-leading power efficiency.
• The position focuses on SoC power estimation and optimization for power-critical wireless products.
• - Work with architects to define power-critical use cases and scenarios.
• - Establish power targets and collaborate with cross-functional teams to achieve optimization goals.
• - Define comprehensive test cases within design verification environments.
• - Generate accurate pre-silicon power estimations for design decision-making.
• - Analyze power consumption patterns and identify optimization opportunities.
• - Develop SoC power models for new architecture designs, enabling performance/power trade-off analysis.
• - Understand software and system-level interactions that impact overall power consumption.
• - Partner with lab and silicon characterization teams to correlate models with measured silicon data.
• Perform comprehensive SoC power simulation and analysis using PtPx and PPRTL tools across multiple wireless use cases and operating scenarios.
• Develop and maintain accurate power models for new wireless SoC architectures, enabling early power-performance trade-off analysis during design phases.
• Collaborate with silicon design teams, architects, and verification engineers to define power-critical test scenarios and establish realistic power targets for wireless connectivity features.
• Drive pre-silicon power estimation and post-silicon correlation activities, working closely with Silicon validation teams to validate and refine power models against measured silicon data.
• Identify and quantify power optimization opportunities across architecture, RTL, and physical implementation levels, providing actionable recommendations to design teams.
• Analyze system-level power interactions between wireless subsystems and other SoC components to optimize overall power efficiency.
• Create and maintain automated power analysis flows and methodologies to support multiple concurrent SoC development programs.
• Present power analysis results and optimization strategies to cross-functional teams and senior leadership.

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