CAD Engineer, Silicon Learning and Static Timing Analysis
Apple
CAD Engineer, Silicon Learning and Static Timing Analysis
Job Description
Do you love tackling highly complex challenges with a keen eye towards revealing what has been hidden to others? Do you intrinsically understand the difference between correlation and causation? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) working on leading edge semiconductor technology nodes where the hidden details make a real difference in performance, power, and area. Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices and things that they haven’t yet imagined possible. In this critical role, you will be responsible for analyzing silicon performance data and incorporating the learnings back into static timing analysis tools, flows, margins, and design closure methodologies to drive continuous improvements in Apple products. You will help refine our understanding of advanced silicon to truly optimize performance and battery life in phones, laptops, and products not yet dreamt of. • Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon design at Apple. • Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis • Develop and deploy design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products
Locations
- Austin, Texas, United States 78727
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analyzing silicon performance dataintermediate
- static timing analysisintermediate
- design closure methodologiesintermediate
- data miningintermediate
- data analysisintermediate
- establishing correlation metricsintermediate
- developing design closure marginsintermediate
- deploying design methodologiesintermediate
- optimizing power/performance tradeoffsintermediate
- designing experimentsintermediate
- analyzing resultsintermediate
- refining design methodologiesintermediate
Required Qualifications
- Minimum requirement of BS + 10 years of relevant industry experience (experience, 10 years)
- Coding experience in one or more of C, Perl, Python, or Tcl (experience)
Preferred Qualifications
- Experience working in static timing analysis, DFT, physical design, failure analysis or CAD (experience)
- Static Timing Analysis with Primetime, Tempus, or equivalent (experience)
- Solid C, Perl, Python or Tcl coding/debug skills coupled with an understanding of the design challenges in advanced technology nodes (experience)
- Fundamentals of statistics, hypothesis testing, data mining, Machine Learning and Design of Experiments. (experience)
- Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing is a plus. (experience)
Responsibilities
- * Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon design at Apple.
- * Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis
- * Develop and deploy design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products
Tags & Categories
Answer 10 quick questions to check your fit for CAD Engineer, Silicon Learning and Static Timing Analysis @ Apple.
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CAD Engineer, Silicon Learning and Static Timing Analysis
Apple
CAD Engineer, Silicon Learning and Static Timing Analysis
Job Description
Do you love tackling highly complex challenges with a keen eye towards revealing what has been hidden to others? Do you intrinsically understand the difference between correlation and causation? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) working on leading edge semiconductor technology nodes where the hidden details make a real difference in performance, power, and area. Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices and things that they haven’t yet imagined possible. In this critical role, you will be responsible for analyzing silicon performance data and incorporating the learnings back into static timing analysis tools, flows, margins, and design closure methodologies to drive continuous improvements in Apple products. You will help refine our understanding of advanced silicon to truly optimize performance and battery life in phones, laptops, and products not yet dreamt of. • Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon design at Apple. • Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis • Develop and deploy design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products
Locations
- Austin, Texas, United States 78727
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analyzing silicon performance dataintermediate
- static timing analysisintermediate
- design closure methodologiesintermediate
- data miningintermediate
- data analysisintermediate
- establishing correlation metricsintermediate
- developing design closure marginsintermediate
- deploying design methodologiesintermediate
- optimizing power/performance tradeoffsintermediate
- designing experimentsintermediate
- analyzing resultsintermediate
- refining design methodologiesintermediate
Required Qualifications
- Minimum requirement of BS + 10 years of relevant industry experience (experience, 10 years)
- Coding experience in one or more of C, Perl, Python, or Tcl (experience)
Preferred Qualifications
- Experience working in static timing analysis, DFT, physical design, failure analysis or CAD (experience)
- Static Timing Analysis with Primetime, Tempus, or equivalent (experience)
- Solid C, Perl, Python or Tcl coding/debug skills coupled with an understanding of the design challenges in advanced technology nodes (experience)
- Fundamentals of statistics, hypothesis testing, data mining, Machine Learning and Design of Experiments. (experience)
- Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing is a plus. (experience)
Responsibilities
- * Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon design at Apple.
- * Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis
- * Develop and deploy design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products
Tags & Categories
Answer 10 quick questions to check your fit for CAD Engineer, Silicon Learning and Static Timing Analysis @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs