CAD Engineer - Timing for Gate-Level Flows & Methodologies
Apple
CAD Engineer - Timing for Gate-Level Flows & Methodologies
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon. As a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
Locations
- Austin, Texas, United States 78727
- San Jose, California, United States 95112
Salary
Skills Required
- static timing analysis (STA)intermediate
- gate-level STA flowsintermediate
- developing flows and methodologiesintermediate
- debugging issues related to constraints and flow scriptsintermediate
- timing closureintermediate
- STA methodology changesintermediate
- developing scripts and methods for timing analysisintermediate
- power reduction methodologiesintermediate
- verification of timing constraintsintermediate
- analysis of timing pathsintermediate
- post-silicon timing debugintermediate
- working with EDA vendorsintermediate
- driving best practicesintermediate
Required Qualifications
- Minimum requirement of BS and 3 years of relevant industry experience. (experience, 3 years)
Preferred Qualifications
- Experience with static timing analysis tools and flows (experience)
- Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages (experience)
- Familiar with STA of large high-performance SoC designs in deep sub-micron technologies (experience)
- Understanding of fundamentals in noise, cross-talk, variation and timing margins (experience)
- Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus (experience)
- Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion (experience)
Responsibilities
- As a member of our STA CAD team, you will:
- • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
- • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
- • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
- • Develop and maintain scripts and methods for timing analysis and power reduction
- • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
- • Analysis of timing paths to identify key issues, including post-silicon timing debug
- • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
Tags & Categories
Answer 10 quick questions to check your fit for CAD Engineer - Timing for Gate-Level Flows & Methodologies @ Apple.
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~2 Minutes
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CAD Engineer - Timing for Gate-Level Flows & Methodologies
Apple
CAD Engineer - Timing for Gate-Level Flows & Methodologies
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon. As a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
Locations
- Austin, Texas, United States 78727
- San Jose, California, United States 95112
Salary
Skills Required
- static timing analysis (STA)intermediate
- gate-level STA flowsintermediate
- developing flows and methodologiesintermediate
- debugging issues related to constraints and flow scriptsintermediate
- timing closureintermediate
- STA methodology changesintermediate
- developing scripts and methods for timing analysisintermediate
- power reduction methodologiesintermediate
- verification of timing constraintsintermediate
- analysis of timing pathsintermediate
- post-silicon timing debugintermediate
- working with EDA vendorsintermediate
- driving best practicesintermediate
Required Qualifications
- Minimum requirement of BS and 3 years of relevant industry experience. (experience, 3 years)
Preferred Qualifications
- Experience with static timing analysis tools and flows (experience)
- Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages (experience)
- Familiar with STA of large high-performance SoC designs in deep sub-micron technologies (experience)
- Understanding of fundamentals in noise, cross-talk, variation and timing margins (experience)
- Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus (experience)
- Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion (experience)
Responsibilities
- As a member of our STA CAD team, you will:
- • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
- • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
- • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
- • Develop and maintain scripts and methods for timing analysis and power reduction
- • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
- • Analysis of timing paths to identify key issues, including post-silicon timing debug
- • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
Tags & Categories
Answer 10 quick questions to check your fit for CAD Engineer - Timing for Gate-Level Flows & Methodologies @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs