Job Description

Locations

• Munich, Bavaria-Bayern, Germany 80335

Salary

Skills Required

• developing hardware IPsintermediate
• digital signal processingintermediate
• integrating IPs into SoCsintermediate
• design verificationintermediate
• silicon validationintermediate
• STAintermediate
• DFTintermediate
• power optimizationsintermediate
• timing closureintermediate
• physical designintermediate
• analog designintermediate
• firmware designintermediate
• system designintermediate

Required Qualifications

• Experienced with crafting low-power customized hardware for digital signal processing. Understanding of signal processing principles. Abstract modeling skills for synthesis and simulation using modern modeling language. (Verilog / System Verilog). (experience)
• Hands-on experience in multiple sophisticated ASIC or FPGA designs, spanning from concept to productization. (experience)
• Hands-on experience with digital logic design and quality checks, such as Lint and CDC/RDC. (experience)
• Proficient in using (System)Verilog, the ability to analyze RTL/Netlist designs, and outstanding debugging skills to solve technical challenges. (experience)
• Familiar with day-to-day usage of scripting languages (e.g., TCL, Python, Perl, shell), Linux, and revision control systems (e.g., Perforce), database management, and releases. (experience)
• Passion for owning/driving design topics using well-defined metrics, a strong initiative, and ownership of responsibilities, productive, and able to meet daring deadlines. (experience)
• Very good interpersonal skills and the ability to communicate abstract concepts to different stakeholders. Excellent problem-solving skills and the ability to find effective technical solutions between partners in RTL design, Firmware, System Engineering, Power, and Physical Design teams. (experience)
• English language proficiency is a requirement for this position. (experience)

Preferred Qualifications

• Experience with on-chip communication buses & fabrics like AMBA/Wishbone and processor sub-systems would be a plus. (experience)
• Experience with SystemC/C++ hardware design modeling, high-level synthesis, and logical synthesis would be desirable. (experience)
• A master’s or Ph.D. in electrical engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent, paired with several years of industry work experience. (experience)
• Apple is an equal-opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. (experience)

Responsibilities

• As a Cellular design engineer, you will be developing, integrating & verifying IP sub-components for a cellular transceiver System on a Chip. You would be responsible for defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary group from system, digital, analog & firmware design, to design verification, and physical design teams, which will support your daily work.
• Your work will not be limited to design. It will cover end-to-end responsibility across the project lifecycle for the IPs developed from concept to design, verification, integration, silicon validation, and finally, in-field operation.

Tags & Categories