Job Description

Locations

• San Diego, California, United States 92128
• Sunnyvale, California, United States 94085

Salary

Skills Required

• timing constraints generationintermediate
• timing analysisintermediate
• timing closureintermediate
• SOC designintermediate
• full chip timing closureintermediate
• block level timing closureintermediate
• generation of timing constraintsintermediate
• timing sign-offintermediate
• resolving timing issuesintermediate
• ASIC STA engineeringintermediate

Required Qualifications

• BS and 10+ years of relevant industry experience. (experience, 10 years)
• Hands-on experience in ASIC timing constraints generation and timing closure. (experience)
• Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing. (experience)
• Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing. (experience)
• Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer). (experience)
• Knowledge of timing corners/modes, process variations and signal integrity related issues. (experience)
• Hands on experience in timing/SDC constraints generation and management. (experience)
• Proficient in scripting languages (Tcl and Perl/Python). (experience)
• Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of diverse groups (e.g. digital design, DFT, physical design, etc.). (experience)

Preferred Qualifications

• MS and 8+ years of relevant industry experience. (experience, 8 years)
• Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired. (experience)
• Solid understanding of low-power techniques including clock gating, power gating and multi-voltage designs. (experience)

Responsibilities

• As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of complex SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.
• As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple corners and modes using tools like Synopsys PrimeTime.
• The role includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues.
• Own STA sign-off for block and chip level including custom timing checks. Develop automation scripts in Tcl or Python to streamline analysis and reporting, prepare sign-off quality constraints, and ensure the design meets all performance and reliability targets before tape-out.
• Own STA sign-off for block and chip level including custom timing checks.

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