CPU CDC/STA Engineer
Apple
CPU CDC/STA Engineer
Job Description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! As a CPU CDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems • Working closely with EDA vendor representatives to drive improvements and new methodologies • Working closely with RTL, Verification, CAD, and Physical Design teams
Locations
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analyzing the designintermediate
- driving fixesintermediate
- developing constraintsintermediate
- maintaining constraintsintermediate
- improving constraintsintermediate
- developing methodologyintermediate
- maintaining methodologyintermediate
- improving methodologyintermediate
- developing CDC sign-offsintermediate
- improving CDC sign-offsintermediate
- maintaining CDC sign-offsintermediate
- developing RDC sign-offsintermediate
- improving RDC sign-offsintermediate
- maintaining RDC sign-offsintermediate
- recommending System Verilog assertionsintermediate
- developing STA checksintermediate
- enhancing STA checksintermediate
- maintaining STA checksintermediate
- developing STA sign-offsintermediate
- enhancing STA sign-offsintermediate
- maintaining STA sign-offsintermediate
- debugging vendor tool problemsintermediate
- collaborating with designersintermediate
- collaborating with EDA vendor representativesintermediate
- driving improvementsintermediate
- driving new methodologiesintermediate
- working with RTL teamsintermediate
- working with DV teamsintermediate
- working with Verification teamsintermediate
- working with CAD teamsintermediate
- working with Physical Design teamsintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
- Scripting skills in Tcl or Perl (experience)
- Experience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions (experience)
- Experience in Verilog (experience)
Preferred Qualifications
- Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations (experience)
- Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus (experience)
Responsibilities
- In this role, you will be:
- • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
- • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
- • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs
- • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
- • Working closely with EDA vendor representatives to drive improvements and new methodologies
- • Working closely with RTL, Verification, CAD, and Physical Design teams
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Answer 10 quick questions to check your fit for CPU CDC/STA Engineer @ Apple.
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CPU CDC/STA Engineer
Apple
CPU CDC/STA Engineer
Job Description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! As a CPU CDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems • Working closely with EDA vendor representatives to drive improvements and new methodologies • Working closely with RTL, Verification, CAD, and Physical Design teams
Locations
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- analyzing the designintermediate
- driving fixesintermediate
- developing constraintsintermediate
- maintaining constraintsintermediate
- improving constraintsintermediate
- developing methodologyintermediate
- maintaining methodologyintermediate
- improving methodologyintermediate
- developing CDC sign-offsintermediate
- improving CDC sign-offsintermediate
- maintaining CDC sign-offsintermediate
- developing RDC sign-offsintermediate
- improving RDC sign-offsintermediate
- maintaining RDC sign-offsintermediate
- recommending System Verilog assertionsintermediate
- developing STA checksintermediate
- enhancing STA checksintermediate
- maintaining STA checksintermediate
- developing STA sign-offsintermediate
- enhancing STA sign-offsintermediate
- maintaining STA sign-offsintermediate
- debugging vendor tool problemsintermediate
- collaborating with designersintermediate
- collaborating with EDA vendor representativesintermediate
- driving improvementsintermediate
- driving new methodologiesintermediate
- working with RTL teamsintermediate
- working with DV teamsintermediate
- working with Verification teamsintermediate
- working with CAD teamsintermediate
- working with Physical Design teamsintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
- Scripting skills in Tcl or Perl (experience)
- Experience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions (experience)
- Experience in Verilog (experience)
Preferred Qualifications
- Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations (experience)
- Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus (experience)
Responsibilities
- In this role, you will be:
- • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
- • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
- • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs
- • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
- • Working closely with EDA vendor representatives to drive improvements and new methodologies
- • Working closely with RTL, Verification, CAD, and Physical Design teams
Tags & Categories
Answer 10 quick questions to check your fit for CPU CDC/STA Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs