CPU Debug and Power Management Verification Engineer
Apple
CPU Debug and Power Management Verification Engineer
Job Description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers—spanning both ARM-standard capabilities and Apple-specific innovations. • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs. • Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic • Develop and execute test plans and schedules • Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments • Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors. • Analyze functional coverage to ensure test plan completeness • Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes • Support SoC-level debug for clock and power integration issues • Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.
Locations
- Beaverton, Oregon, United States 97005
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Design Verificationintermediate
- chip designintermediate
- ARM-based CPUintermediate
- Power Managementintermediate
- Clock Controlintermediate
- Debug Infrastructureintermediate
- Resetsintermediate
- Special-Purpose Registersintermediate
- pre-silicon test planningintermediate
- post-silicon bring-upintermediate
- post-silicon debugintermediate
- RTL designintermediate
- test plan developmentintermediate
- test executionintermediate
- Assembly programmingintermediate
- SystemVerilogintermediate
- SVAintermediate
- C++ programmingintermediate
- scripting languagesintermediate
- simulationintermediate
- emulationintermediate
- FPGAintermediate
- verification infrastructureintermediate
- checkersintermediate
- transactorsintermediate
- coverage monitorsintermediate
- functional coverage analysisintermediate
- root-cause analysisintermediate
- design issue documentationintermediate
- SoC-level debugintermediate
- clock integrationintermediate
- power integrationintermediate
- silicon bring-upintermediate
- waveform analysisintermediate
- trace toolsintermediate
- system debugintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
- Programming skills in Perl/Python or SystemVerilog (experience)
Preferred Qualifications
- Experience in processor or power management architecture and verification (experience)
- Experience with system fabric protocols such as AXI (experience)
- In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches (experience)
- Experience in system Verilog assertions or silicon bringup or UPF and low power simulation (experience)
- Experience in processor debug features including hardware trace is a plus (experience)
- Experience with advanced verification techniques such as formal verification is a plus (experience)
- Advanced programming skills such as object orientated programming or CPU assembly language is a plus (experience)
- Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort (experience)
- Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design (experience)
Responsibilities
- We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers—spanning both ARM-standard capabilities and Apple-specific innovations.
- • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs.
- • Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic
- • Develop and execute test plans and schedules
- • Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments
- • Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors.
- • Analyze functional coverage to ensure test plan completeness
- • Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes
- • Support SoC-level debug for clock and power integration issues
- • Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.
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CPU Debug and Power Management Verification Engineer
Apple
CPU Debug and Power Management Verification Engineer
Job Description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers—spanning both ARM-standard capabilities and Apple-specific innovations. • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs. • Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic • Develop and execute test plans and schedules • Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments • Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors. • Analyze functional coverage to ensure test plan completeness • Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes • Support SoC-level debug for clock and power integration issues • Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.
Locations
- Beaverton, Oregon, United States 97005
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Design Verificationintermediate
- chip designintermediate
- ARM-based CPUintermediate
- Power Managementintermediate
- Clock Controlintermediate
- Debug Infrastructureintermediate
- Resetsintermediate
- Special-Purpose Registersintermediate
- pre-silicon test planningintermediate
- post-silicon bring-upintermediate
- post-silicon debugintermediate
- RTL designintermediate
- test plan developmentintermediate
- test executionintermediate
- Assembly programmingintermediate
- SystemVerilogintermediate
- SVAintermediate
- C++ programmingintermediate
- scripting languagesintermediate
- simulationintermediate
- emulationintermediate
- FPGAintermediate
- verification infrastructureintermediate
- checkersintermediate
- transactorsintermediate
- coverage monitorsintermediate
- functional coverage analysisintermediate
- root-cause analysisintermediate
- design issue documentationintermediate
- SoC-level debugintermediate
- clock integrationintermediate
- power integrationintermediate
- silicon bring-upintermediate
- waveform analysisintermediate
- trace toolsintermediate
- system debugintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
- Programming skills in Perl/Python or SystemVerilog (experience)
Preferred Qualifications
- Experience in processor or power management architecture and verification (experience)
- Experience with system fabric protocols such as AXI (experience)
- In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches (experience)
- Experience in system Verilog assertions or silicon bringup or UPF and low power simulation (experience)
- Experience in processor debug features including hardware trace is a plus (experience)
- Experience with advanced verification techniques such as formal verification is a plus (experience)
- Advanced programming skills such as object orientated programming or CPU assembly language is a plus (experience)
- Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort (experience)
- Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design (experience)
Responsibilities
- We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers—spanning both ARM-standard capabilities and Apple-specific innovations.
- • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs.
- • Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic
- • Develop and execute test plans and schedules
- • Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments
- • Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors.
- • Analyze functional coverage to ensure test plan completeness
- • Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes
- • Support SoC-level debug for clock and power integration issues
- • Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.
Tags & Categories
Answer 10 quick questions to check your fit for CPU Debug and Power Management Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs