Job Description

Locations

• Santa Clara, California, United States 95050

Salary

Skills Required

• collaborating with teamsintermediate
• verifying functionality correctnessintermediate
• developing test plansintermediate
• executing test plansintermediate
• developing tests in Assemblyintermediate
• developing tests in Scriptsintermediate
• developing tests in System Verilogintermediate
• developing tests in vectorsintermediate
• driving testing in simulationintermediate
• driving testing in emulationintermediate
• root cause analysisintermediate
• proposing solutionsintermediate
• developing tests for emulationintermediate
• developing tests for FPGAintermediate
• aiding silicon debugintermediate
• developing coverage monitorsintermediate
• analyzing coverageintermediate
• developing checkersintermediate
• developing Verilog-based transactorintermediate
• developing System Verilog-based transactorintermediate
• writing assertionsintermediate
• applying formal verificationintermediate

Required Qualifications

• Minimum BS (experience)
• Academic experience in computer architecture (experience)
• Academic experience in digital design using Verilog (experience)

Preferred Qualifications

• Master’s degree preferred (degree)
• Knowledge of digital logic, micro-processor architecture and power management architecture (experience)
• Proficiency in programming and scripting in Python, or Perl, or TCL (experience)
• Experience or academic knowledge in design verification methodology. Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers (experience)
• Knowledge of system Verilog assertions or other advance verification techniques such as formal verification is a plus (experience)
• Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification efforts (experience)
• Be able to follow detailed work schedules and work independently on the verification efforts for a block/area of the design (experience)

Responsibilities

• As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows:
• • Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
• • Develop and execute test plans and schedules for the power management and clock control logic
• • Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
• • Root cause failures and propose potential solution to the design team
• • Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design
• • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
• • Develop checkers or Verilog/System Verilog-base transactor to verify the design
• • Write assertions and apply formal verification to the design

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