Job Description

Locations

• Santa Clara, California, United States 95050

Salary

Skills Required

• verifying functionality correctnessintermediate
• developing test plansintermediate
• executing test plansintermediate
• developing tests in Assemblyintermediate
• developing tests in Scriptsintermediate
• developing tests in System Verilogintermediate
• developing tests in vectorsintermediate
• driving testing in simulation environmentsintermediate
• driving testing in emulation environmentsintermediate
• root cause analysisintermediate
• proposing solutionsintermediate
• developing tests for emulation and FPGA environmentsintermediate
• aiding silicon debugintermediate
• developing coverage monitorsintermediate
• analyzing coverageintermediate
• developing checkersintermediate
• developing Verilog-based transactorintermediate
• developing System Verilog-based transactorintermediate
• writing assertionsintermediate
• applying formal verificationintermediate
• working closely with architecture and RTL designersintermediate
• collaborating with teamsintermediate

Required Qualifications

• Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
• Experience with digital logic, micro-processor architecture, or power management architecture (experience)
• Experience with digital design verification including Verilog/System-Verilog based testbenches and transactors checkers (experience)
• Programming skills in scripting languages such as Perl or Python (experience)

Preferred Qualifications

• Master’s degree preferred (degree)
• Experience in processor or power management architecture and verification (experience)
• In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches (experience)
• Experience in system Verilog assertions or silicon bringup or UPF and low power simulation (experience)
• Experience with advanced verification techniques such as formal verification is a plus (experience)
• Advanced programming skills such as object orientated programming or CPU assembly language is a plus (experience)
• Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort (experience)
• Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design (experience)

Responsibilities

• As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows:
• • Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
• • Develop and execute test plans and schedules for the power management and clock control logic
• • Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
• • Root cause failures and propose potential solution to the design team
• • Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design
• • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
• • Develop checkers or Verilog/System Verilog-base transactor to verify the design
• • Write assertions and apply formal verification to the design

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