Job Description

Locations

• Israel, Israel
• Herzliya, Tel Aviv District, Israel

Salary

Skills Required

• establishing DV methodologyintermediate
• test-plan developmentintermediate
• verification environment developmentintermediate
• stimulus developmentintermediate
• checkers developmentintermediate
• test-writingintermediate
• debugintermediate
• coverage analysisintermediate
• sign-off for RTL freezeintermediate
• sign-off for tape-outintermediate
• understanding cache coherence protocolsintermediate
• Load-Store unit verificationintermediate
• caches verificationintermediate
• bus interface units verificationintermediate
• memory controller verificationintermediate
• developing verification environment for simulationintermediate
• developing verification environment for emulationintermediate
• developing synthesizable transactorsintermediate
• developing test benchesintermediate
• supporting verification hooksintermediate
• developing unit level stimulusintermediate
• developing full chip assembly stimulusintermediate
• developing C programs for verificationintermediate
• developing verification IPsintermediate
• working with CPU/SOC RTLintermediate
• understanding specificationsintermediate
• developing verification strategyintermediate
• system level considerationsintermediate
• developing coverage monitorsintermediate
• accomplishing coverage goalsintermediate
• developing abstract end-to-end checksintermediate
• verifying CPU-SOC memory subsystem interactionintermediate
• verifying coherence protocolsintermediate

Required Qualifications

• The ideal candidate should 5+ years of processor verification experience. (experience, 5 years)
• In-depth knowledge of digital logic design, CPU and SOC architecture/micro-architecture and memory subsystem (experience)
• Strong programming (C/C++, Verilog, Scripting), software optimization, and performance improvement skills (experience)
• Experience in unit and full chip level test benches (experience)
• Experience in developing testplans, assertions, and developing stimulus (experience)

Preferred Qualifications

• Should be a team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design (experience)
• Experience with emulation and developing synthesizable transactors is a plus (experience)

Responsibilities

• The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
• Play a critical role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/SOC that are relevant to memory subsystem verification. These units include Load-Store unit, different levels of caches, bus interface units, memory controller, etc.
• Develop verification environment which can be used in both simulation and emulation.
• Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU/SOC features.
• Develop unit level stimulus as well as full chip assembly or C programs to verify memory subsystem functionality.
• Develop verification IPs that can be utilized by Apple teams worldwide
• Work closely with the CPU/SOC RTL spread across US and Israel to understand the specification in detail for developing verification strategy taking system level considerations into account.
• Develop coverage monitors and accomplish coverage goals for closure of the design.
• Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols

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