Job Description

Locations

• Santa Clara, California, United States 95050

Salary

Skills Required

• circuit timing engineeringintermediate
• designing sophisticated circuitsintermediate
• low power circuit designintermediate
• developing timing modelsintermediate
• developing timing methodologyintermediate
• enabling global timing directivesintermediate
• validating transistor level timing accuracyintermediate
• validating timing test correctnessintermediate
• collaborating with cross-functional teamsintermediate
• integrating new insightsintermediate

Required Qualifications

• BS and a minimum of 10 years of relevant industry experience. (experience, 10 years)

Preferred Qualifications

• We are looking for applicants with 10+ years of proven experience in transistor level static timing analysis and noise flows as well as the following: (experience, 10 years)
• Expertise and in depth knowledge of industry standard STA tools, Nanotime and Primetime. (experience)
• Experience in timing constraints generation & management, and timing convergence in the CPU environment. (experience)
• Familiarity with custom memory designs (SRAM/ register file / dynamic circuits). (experience)
• Ability to perform spice simulations for correlation to static timing and noise results. (experience)
• Expertise in analyzing and converging crosstalk delay and noise glitch in deep submicron processes. (experience)
• Good interpersonal skills. (experience)
• Scripting skills for flow automation; experience with tcl is a plus. (experience)
• Knowledge of industry standard circuit and design tools. (experience)
• MSEE preferred (experience)

Responsibilities

• Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, as well as work with a team of hardworking engineers. As a Circuit Timing Engineer for the custom digital team, you will develop timing models and methodology and will perform the following:
• - Enable global directives to ensure proper timing of innovative circuit topologies.
• - Provide a link between circuit designers, tool developers and chip level timing to validate transistor level timing accuracy and timing test correctness.
• - Develop timing methodology that is crucial to support billions of Apple devices providing high performance in a very small power envelope

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