DDR Design Engineer
Apple
DDR Design Engineer
Job Description
At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking DDR Design Engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day! You will join the DDR PHY design team. We provide outstanding PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization. In this role, you will be responsible for: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- concept studyintermediate
- architecture definitionintermediate
- RTL designintermediate
- design verificationintermediate
- silicon bring-upintermediate
- power characterizationintermediate
- writing design specificationsintermediate
- writing test plansintermediate
- RTL descriptionintermediate
- assertionsintermediate
- formal toolsintermediate
- static checkersintermediate
- functional coverageintermediate
- code coverageintermediate
- timing closureintermediate
Required Qualifications
- Bachelors of Science in Electrical Engineering and 3 years experience preferred (experience, 3 years)
Preferred Qualifications
- RTL design using Verilog or SystemVerilog, assertion writing (experience)
- Design of state machines, data paths, arbitration and clock domain crossing logic (experience)
- Logic synthesis, timing constraints (experience)
- Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL (experience)
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking (experience)
- Prior experience in DDR PHY design and mixed-signal environment is a plus (experience)
Responsibilities
- In this role, you will be responsible for: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.
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Answer 10 quick questions to check your fit for DDR Design Engineer @ Apple.
10 Questions
~2 Minutes
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DDR Design Engineer
Apple
DDR Design Engineer
Job Description
At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking DDR Design Engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day! You will join the DDR PHY design team. We provide outstanding PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization. In this role, you will be responsible for: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- concept studyintermediate
- architecture definitionintermediate
- RTL designintermediate
- design verificationintermediate
- silicon bring-upintermediate
- power characterizationintermediate
- writing design specificationsintermediate
- writing test plansintermediate
- RTL descriptionintermediate
- assertionsintermediate
- formal toolsintermediate
- static checkersintermediate
- functional coverageintermediate
- code coverageintermediate
- timing closureintermediate
Required Qualifications
- Bachelors of Science in Electrical Engineering and 3 years experience preferred (experience, 3 years)
Preferred Qualifications
- RTL design using Verilog or SystemVerilog, assertion writing (experience)
- Design of state machines, data paths, arbitration and clock domain crossing logic (experience)
- Logic synthesis, timing constraints (experience)
- Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL (experience)
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking (experience)
- Prior experience in DDR PHY design and mixed-signal environment is a plus (experience)
Responsibilities
- In this role, you will be responsible for: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.
Tags & Categories
Answer 10 quick questions to check your fit for DDR Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs