Debug SoC Design Engineer
Apple
Debug SoC Design Engineer
Job Description
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- designing CPU-based subsystemsintermediate
- SoC architectureintermediate
- IP developmentintermediate
- debug features designintermediate
- debug and trace hub designintermediate
- ASIC debugintermediate
Required Qualifications
- BS with 10+ years relevant experience. (experience, 10 years)
- Familiarity with the ASIC design flow. (experience)
- Knowledge of digital design, SoC architecture, and HDL languages like Verilog. (experience)
- Familiarity with design methodologies and industry standard EDA tools. (experience)
Preferred Qualifications
- Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques. (experience)
- Shown experience writing micro-architecture specifications and converting them to design. (experience)
- Experience with AXI/AHB bus fabric and processor sub-systems. (experience)
- Understanding of UPF and low-power design & implementation techniques. (experience)
- Self-starter and willingness to learn. (experience)
Responsibilities
- In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals.
- You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
- RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance, area and timing goals.
- Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural debug features, develop micro-architectural details, and arrive at a detailed specification.
- Verification - support the verification team in test bench development and simulation/emulation for functional verification of debug features.
- Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or overconsumption.
- Validation - Aid in debug of silicon issues at SoC level by employing the necessary debug features
- Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
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Answer 10 quick questions to check your fit for Debug SoC Design Engineer @ Apple.
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Debug SoC Design Engineer
Apple
Debug SoC Design Engineer
Job Description
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- designing CPU-based subsystemsintermediate
- SoC architectureintermediate
- IP developmentintermediate
- debug features designintermediate
- debug and trace hub designintermediate
- ASIC debugintermediate
Required Qualifications
- BS with 10+ years relevant experience. (experience, 10 years)
- Familiarity with the ASIC design flow. (experience)
- Knowledge of digital design, SoC architecture, and HDL languages like Verilog. (experience)
- Familiarity with design methodologies and industry standard EDA tools. (experience)
Preferred Qualifications
- Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques. (experience)
- Shown experience writing micro-architecture specifications and converting them to design. (experience)
- Experience with AXI/AHB bus fabric and processor sub-systems. (experience)
- Understanding of UPF and low-power design & implementation techniques. (experience)
- Self-starter and willingness to learn. (experience)
Responsibilities
- In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals.
- You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
- RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance, area and timing goals.
- Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural debug features, develop micro-architectural details, and arrive at a detailed specification.
- Verification - support the verification team in test bench development and simulation/emulation for functional verification of debug features.
- Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or overconsumption.
- Validation - Aid in debug of silicon issues at SoC level by employing the necessary debug features
- Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Tags & Categories
Answer 10 quick questions to check your fit for Debug SoC Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs