Design Verification Engineer
Apple
Design Verification Engineer
Job Description
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology organization, and we'd love to have you join us. As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP: - Neural Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1 - Hardware security, including cryptographic algorithm implementations - High-Speed IO standards such as PCI Express, DisplayPort, MIPI - Power management and fabric infrastructure - Memory cache management - Display Subsystem for variety of panels and products. These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!
Locations
- Cupertino, California, United States 95014
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Design Verificationintermediate
- Verifying functionality and performanceintermediate
- Reviewing design and architecture specificationsintermediate
- Collaborating with design and micro-architecture teamsintermediate
- Understanding functional and performance goalsintermediate
- Developing test plansintermediate
- Developing testsintermediate
- Developing coverage plansintermediate
- Defining verification methodologyintermediate
- Developing testbenchesintermediate
- Communicating and collaborating with design teamsintermediate
- Communicating and collaborating with architecture teamsintermediate
- Communicating and collaborating with software teamsintermediate
- Understanding use casesintermediate
- Understanding corner conditionsintermediate
- Driving test casesintermediate
- Neural Engine hardwareintermediate
- DRAM subsystemintermediate
- Memory controller logicintermediate
- Encode systemsintermediate
- Decode systemsintermediate
- ProRes codecintermediate
- VP9 codecintermediate
- AV1 codecintermediate
- Hardware securityintermediate
- Cryptographic algorithm implementationsintermediate
- PCI Expressintermediate
- DisplayPortintermediate
- MIPIintermediate
- Power managementintermediate
- Fabric infrastructureintermediate
- Memory cache managementintermediate
- Display Subsystemintermediate
Required Qualifications
- Minimum of BS + 3 years relevant industry experience. (experience, 3 years)
Preferred Qualifications
- Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy (experience)
- Knowledge of SystemVerilog, digital simulation and debug (experience)
- Knowledge of computer architecture and digital design fundamentals (experience)
- SW programming skills with knowledge of data structures and algorithms (experience)
- Experience with Python, Perl, or similar scripting language (experience)
- Ability to work independently to deliver the project goals (experience)
- Knowledge of verification methodologies like UVM (experience)
- Experience with C/C++, assembly is a plus (experience)
- Excellent interpersonal skills and the dream to tackle diverse challenges. (experience)
Responsibilities
- As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
- The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- - Neural Engine hardware
- - DRAM subsystem, memory controller logic
- - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- - Hardware security, including cryptographic algorithm implementations
- - High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- - Power management and fabric infrastructure
- - Memory cache management
- - Display Subsystem for variety of panels and products.
- These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!
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Design Verification Engineer
Apple
Design Verification Engineer
Job Description
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology organization, and we'd love to have you join us. As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP: - Neural Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1 - Hardware security, including cryptographic algorithm implementations - High-Speed IO standards such as PCI Express, DisplayPort, MIPI - Power management and fabric infrastructure - Memory cache management - Display Subsystem for variety of panels and products. These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!
Locations
- Cupertino, California, United States 95014
- Santa Clara, California, United States 95050
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Design Verificationintermediate
- Verifying functionality and performanceintermediate
- Reviewing design and architecture specificationsintermediate
- Collaborating with design and micro-architecture teamsintermediate
- Understanding functional and performance goalsintermediate
- Developing test plansintermediate
- Developing testsintermediate
- Developing coverage plansintermediate
- Defining verification methodologyintermediate
- Developing testbenchesintermediate
- Communicating and collaborating with design teamsintermediate
- Communicating and collaborating with architecture teamsintermediate
- Communicating and collaborating with software teamsintermediate
- Understanding use casesintermediate
- Understanding corner conditionsintermediate
- Driving test casesintermediate
- Neural Engine hardwareintermediate
- DRAM subsystemintermediate
- Memory controller logicintermediate
- Encode systemsintermediate
- Decode systemsintermediate
- ProRes codecintermediate
- VP9 codecintermediate
- AV1 codecintermediate
- Hardware securityintermediate
- Cryptographic algorithm implementationsintermediate
- PCI Expressintermediate
- DisplayPortintermediate
- MIPIintermediate
- Power managementintermediate
- Fabric infrastructureintermediate
- Memory cache managementintermediate
- Display Subsystemintermediate
Required Qualifications
- Minimum of BS + 3 years relevant industry experience. (experience, 3 years)
Preferred Qualifications
- Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy (experience)
- Knowledge of SystemVerilog, digital simulation and debug (experience)
- Knowledge of computer architecture and digital design fundamentals (experience)
- SW programming skills with knowledge of data structures and algorithms (experience)
- Experience with Python, Perl, or similar scripting language (experience)
- Ability to work independently to deliver the project goals (experience)
- Knowledge of verification methodologies like UVM (experience)
- Experience with C/C++, assembly is a plus (experience)
- Excellent interpersonal skills and the dream to tackle diverse challenges. (experience)
Responsibilities
- As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
- The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- - Neural Engine hardware
- - DRAM subsystem, memory controller logic
- - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- - Hardware security, including cryptographic algorithm implementations
- - High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- - Power management and fabric infrastructure
- - Memory cache management
- - Display Subsystem for variety of panels and products.
- These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!
Tags & Categories
Answer 10 quick questions to check your fit for Design Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs