Design Verification Engineer - Power Management (m/f/d)
Apple
Design Verification Engineer - Power Management (m/f/d)
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
Locations
- Swindon, England, United Kingdom SN5 7XB
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- establishing design verification methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus and checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freeze and tape-outintermediate
- developing verification plansintermediate
- building and maintaining verification test bench components and environmentsintermediate
- generating directed and constrained random testsintermediate
- running simulationsintermediate
- debugging design and environment issuesintermediate
- building functional coverage pointsintermediate
- analyzing coverageintermediate
- improving test environment to target coverage holesintermediate
- crafting automated verification flows for block and chip level verificationintermediate
- knowledge of hardware description languages (VHDL/Verilog)intermediate
- knowledge of hardware verification languages (SystemVerilog/UVM/OVM/VVM)intermediate
- knowledge of logic simulatorsintermediate
- verifying complex designsintermediate
- collaboration with Digital and Analog Design engineersintermediate
Required Qualifications
- Strong knowledge of SystemVerilog and UVM (experience)
- Experience developing scalable and portable test-benches (experience)
- Experience with constrained random verification environments (experience)
- MS/BS in Computer Science or Electrical Engineering or equivalent (experience)
- Fluency in English language is required (experience)
Preferred Qualifications
- Experience defining coverage space, writing coverage model, analyzing results (experience)
- Experience with Assertion Based Verification (experience)
- Knowledge of Object Oriented Programming (experience)
- Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification) (experience)
- Experience with Python, Perl or TCL (experience)
- Excellent communication and interpersonal skills combined with the ability to collaborate (experience)
- Basic knowledge of mixed signal verification (experience)
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants (experience)
Responsibilities
- In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
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Answer 10 quick questions to check your fit for Design Verification Engineer - Power Management (m/f/d) @ Apple.
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Design Verification Engineer - Power Management (m/f/d)
Apple
Design Verification Engineer - Power Management (m/f/d)
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
Locations
- Swindon, England, United Kingdom SN5 7XB
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- establishing design verification methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus and checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freeze and tape-outintermediate
- developing verification plansintermediate
- building and maintaining verification test bench components and environmentsintermediate
- generating directed and constrained random testsintermediate
- running simulationsintermediate
- debugging design and environment issuesintermediate
- building functional coverage pointsintermediate
- analyzing coverageintermediate
- improving test environment to target coverage holesintermediate
- crafting automated verification flows for block and chip level verificationintermediate
- knowledge of hardware description languages (VHDL/Verilog)intermediate
- knowledge of hardware verification languages (SystemVerilog/UVM/OVM/VVM)intermediate
- knowledge of logic simulatorsintermediate
- verifying complex designsintermediate
- collaboration with Digital and Analog Design engineersintermediate
Required Qualifications
- Strong knowledge of SystemVerilog and UVM (experience)
- Experience developing scalable and portable test-benches (experience)
- Experience with constrained random verification environments (experience)
- MS/BS in Computer Science or Electrical Engineering or equivalent (experience)
- Fluency in English language is required (experience)
Preferred Qualifications
- Experience defining coverage space, writing coverage model, analyzing results (experience)
- Experience with Assertion Based Verification (experience)
- Knowledge of Object Oriented Programming (experience)
- Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification) (experience)
- Experience with Python, Perl or TCL (experience)
- Excellent communication and interpersonal skills combined with the ability to collaborate (experience)
- Basic knowledge of mixed signal verification (experience)
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants (experience)
Responsibilities
- In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
Tags & Categories
Answer 10 quick questions to check your fit for Design Verification Engineer - Power Management (m/f/d) @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs