Design Verification Engineer
Apple
Design Verification Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- design verification engineeringintermediate
- establishing DV methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus developmentintermediate
- checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freezeintermediate
- sign-off for tape-outintermediate
- developing detailed test plansintermediate
- developing detailed coverage plansintermediate
- developing verification methodologyintermediate
- ensuring scalable environmentintermediate
- ensuring portable environmentintermediate
- assertions developmentintermediate
- trackers developmentintermediate
- mindset to break the designintermediate
- implementing verification plansintermediate
- design bring-upintermediate
- DV environment bring-upintermediate
- regression enablingintermediate
- debug of test failuresintermediate
- developing block-level test-benchesintermediate
- developing IP-level test-benchesintermediate
- developing SoC-level test-benchesintermediate
- tracking DV progressintermediate
- reporting DV progressintermediate
- using metrics (bugs and coverage)intermediate
- use of LLM technologiesintermediate
- use of related technologiesintermediate
Required Qualifications
- BS degree in technical subject area with minimum 3 years of proven experience or equivalent (experience, 3 years)
Preferred Qualifications
- Strong knowledge of OOP, SystemVerilog and UVM (experience)
- Strong knowledge in developing scalable and portable test-benches (experience)
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations (experience)
- Some working experience using LLMs for efficiency and quality (experience)
- Experience with power-aware (UPF) or similar verification methodology (experience)
- Knowledge of one of the scripting languages such as Python, Perl, TCL (experience)
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required (experience)
- Knowledge of formal verification methodology is a plus but not required (experience)
- Knowledge of emulation for verification technologies is a plus but not required (experience)
Responsibilities
- In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
- Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
- Study design specification and create test plan
- Develop infrastructure in SystemVerilog/UVM to stress the design
- Develop and fix failures from regressions, close bugs
- Use LLMs to do verification efficiently
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Answer 10 quick questions to check your fit for Design Verification Engineer @ Apple.
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Design Verification Engineer
Apple
Design Verification Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- design verification engineeringintermediate
- establishing DV methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus developmentintermediate
- checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freezeintermediate
- sign-off for tape-outintermediate
- developing detailed test plansintermediate
- developing detailed coverage plansintermediate
- developing verification methodologyintermediate
- ensuring scalable environmentintermediate
- ensuring portable environmentintermediate
- assertions developmentintermediate
- trackers developmentintermediate
- mindset to break the designintermediate
- implementing verification plansintermediate
- design bring-upintermediate
- DV environment bring-upintermediate
- regression enablingintermediate
- debug of test failuresintermediate
- developing block-level test-benchesintermediate
- developing IP-level test-benchesintermediate
- developing SoC-level test-benchesintermediate
- tracking DV progressintermediate
- reporting DV progressintermediate
- using metrics (bugs and coverage)intermediate
- use of LLM technologiesintermediate
- use of related technologiesintermediate
Required Qualifications
- BS degree in technical subject area with minimum 3 years of proven experience or equivalent (experience, 3 years)
Preferred Qualifications
- Strong knowledge of OOP, SystemVerilog and UVM (experience)
- Strong knowledge in developing scalable and portable test-benches (experience)
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations (experience)
- Some working experience using LLMs for efficiency and quality (experience)
- Experience with power-aware (UPF) or similar verification methodology (experience)
- Knowledge of one of the scripting languages such as Python, Perl, TCL (experience)
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required (experience)
- Knowledge of formal verification methodology is a plus but not required (experience)
- Knowledge of emulation for verification technologies is a plus but not required (experience)
Responsibilities
- In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
- Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
- Study design specification and create test plan
- Develop infrastructure in SystemVerilog/UVM to stress the design
- Develop and fix failures from regressions, close bugs
- Use LLMs to do verification efficiently
Tags & Categories
Answer 10 quick questions to check your fit for Design Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs