Job Description

Locations

• Beaverton, Oregon, United States 97005

Salary

Skills Required

• crafting new solutionsintermediate
• applying engineering fundamentalsintermediate
• designing state-of-the-art ASICsintermediate
• designing custom digital macrosintermediate
• designing custom digital librariesintermediate
• working in fast-paced environmentintermediate
• collaborating with integration teamsintermediate
• collaborating with CAD teamsintermediate
• collaborating with circuit engineering teamsintermediate
• collaborating with technology engineering teamsintermediate
• SOC designintermediate
• integrating new ideasintermediate
• designing complex custom layout for digital circuitsintermediate
• deep SubMicron CMOS technologiesintermediate
• reviewing floorplansintermediate
• analyzing complex circuitsintermediate
• running layout design verification toolsintermediate
• planning workintermediate
• scheduling workintermediate
• negotiating layout tradeoffsintermediate
• interpreting LVS reportsintermediate
• interpreting DRC reportsintermediate
• interpreting ERC reportsintermediate
• using advanced CAD toolsintermediate
• mask design knowledgeintermediate
• layout correctionsintermediate
• robust physical design representationintermediate
• exceeding engineering specificationsintermediate

Required Qualifications

• Bachelors degree in relevant field of study + 3 years of relevant experience. (experience, 3 years)

Preferred Qualifications

• We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits. (experience)
• High level proficiency in layout floorplanning, standard cell planning and hierarchical layout assembly. (experience)
• Good understanding of issues with RC delay, electromigration, self heating and cross capacitance. (experience)
• Recognize failure prone layout structures, dedicatedly work with designers for the best approach to problems. (experience)
• Excellent communication skills and able to work with multi-functional teams. (experience)
• Great skills on interpretation of CALIBRE DRC, ERC, LVS, etc. reports. (experience)
• Knowledge of MENTOR GRAPHICS or CADENCE layout tools (experience)
• Scripting skills in CSH, PERL or SKILL are considered a plus, but not required. (experience)
• Experience in layout automation is considered a plus, but not required. (experience)
• Experience in memory compiler development is considered a plus, but not required. (experience)
• Experience designing low noise, low power datapaths or Memory layout structures, etc. (experience)

Responsibilities

• Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly.
• You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following:
• - Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.
• - Reviewing and analyzing floorplans and complex circuits with circuit designers.
• - Running a complete set of layout design verification tools available on megacells completed.
• - Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
• - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts.
• - Exceed engineering specifications and expectations.
• - Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.

Tags & Categories