Job Description

Locations

• San Diego, California, United States 92128
• Sunnyvale, California, United States 94085
• Waltham, Massachusetts, United States 02453

Salary

Skills Required

• energy-efficient designintermediate
• RF/Analog architecture and designintermediate
• Systems/PHY/MAC architecture and designintermediate
• VLSI/RTL design and integrationintermediate
• Emulationintermediate
• Design Verificationintermediate
• Test and Validationintermediate
• FW/SW engineeringintermediate
• RTL designintermediate
• CAD flows developmentintermediate
• UPFintermediate
• DFTintermediate
• Physical designintermediate
• timing closureintermediate
• ASIC creationintermediate
• collaborationintermediate
• interfacing with multi-disciplinary teamsintermediate

Required Qualifications

• BS and a minimum of 10 years relevant industry experience. (experience, 10 years)
• Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist. (experience)
• Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools. (experience)
• Proficient in scripting in TCL, Perl or Python. (experience)
• Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team for timing fixes and functional ECOs. (experience)

Preferred Qualifications

• Hands-on experience in timing/SDC constraints generation, analysis, and management. (experience)
• Knowledge of timing corners, operating conditions, process variations, and signal integrity-related issues. (experience)
• Knowledge of Place and Route steps including floor planning, CTS, Routing and timing ECOs. (experience)
• Understanding of UPF and low-power design and implementation techniques. (experience)
• Understanding of DFT methodologies including Scan and BIST. (experience)

Responsibilities

• In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple’s products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading-edge products launched to delight millions of customers.
• Generate chip or block level static timing constraints.
• Synthesize design with UPF/DFT/BIST.
• Close timing on critical blocks by working with design and PD teams.
• Perform timing optimization and implement the design for functionality.
• Generate and implement functional ECOs.
• Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers.
• Participate in establishing/improving CAD and design flow methodologies.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.

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