Formal Verification Engineer
Apple
Formal Verification Engineer
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: - Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification - Developing comprehensive formal verification test plan that includes unique security requirement verification - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. - Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures - Developing and implementing re-usable and optimized formal models and verification code base - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- formal verificationintermediate
- developing formal micro-architecture specificationintermediate
- developing comprehensive formal verification test planintermediate
- proving properties of the designintermediate
- finding design bugsintermediate
- working closely with design teamsintermediate
- crafting novel and creative solutionsintermediate
- modelling security attacksintermediate
- proving robustness of complex design micro-architecturesintermediate
- developing and implementing re-usable and optimized formal modelsintermediate
- developing and implementing verification code baseintermediate
- architecting correct-by-construction design methodologiesintermediate
Required Qualifications
- A minimum of a BS degree and a minimum of 10 years of relevant industry experience in silicon validation software engineering or related field. (experience, 10 years)
Preferred Qualifications
- Hands on experience with VLSI and digital logic design and verification techniques or formal methods and their application to hardware, software, or systems (experience)
- Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs (experience)
- Detail oriented approach and desire to overcome challenges is required. (experience)
- Formal Method or Formal Verification technologies knowledge is a plus. (experience)
- Knowledge and experience in interpreting hardware specifications (experience)
- Temporal logic assertion-based languages such as SVA or PSL. (experience)
- Experience in using EDA formal tools and tool development experience is plus. (experience)
- Proficiency in any scripting language with excellent debugging skills. (experience)
- Excellent interpersonal skills. (experience)
- Passionate about developing world-class/innovative formal verification solutions. (experience)
- Exposure to CPU instruction-set architectures, memory consistency or cache coherence principles. (experience)
Responsibilities
- As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for:
- - Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification
- - Developing comprehensive formal verification test plan that includes unique security requirement verification
- - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture.
- - Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures
- - Developing and implementing re-usable and optimized formal models and verification code base
- - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
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Formal Verification Engineer
Apple
Formal Verification Engineer
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: - Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification - Developing comprehensive formal verification test plan that includes unique security requirement verification - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. - Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures - Developing and implementing re-usable and optimized formal models and verification code base - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- formal verificationintermediate
- developing formal micro-architecture specificationintermediate
- developing comprehensive formal verification test planintermediate
- proving properties of the designintermediate
- finding design bugsintermediate
- working closely with design teamsintermediate
- crafting novel and creative solutionsintermediate
- modelling security attacksintermediate
- proving robustness of complex design micro-architecturesintermediate
- developing and implementing re-usable and optimized formal modelsintermediate
- developing and implementing verification code baseintermediate
- architecting correct-by-construction design methodologiesintermediate
Required Qualifications
- A minimum of a BS degree and a minimum of 10 years of relevant industry experience in silicon validation software engineering or related field. (experience, 10 years)
Preferred Qualifications
- Hands on experience with VLSI and digital logic design and verification techniques or formal methods and their application to hardware, software, or systems (experience)
- Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs (experience)
- Detail oriented approach and desire to overcome challenges is required. (experience)
- Formal Method or Formal Verification technologies knowledge is a plus. (experience)
- Knowledge and experience in interpreting hardware specifications (experience)
- Temporal logic assertion-based languages such as SVA or PSL. (experience)
- Experience in using EDA formal tools and tool development experience is plus. (experience)
- Proficiency in any scripting language with excellent debugging skills. (experience)
- Excellent interpersonal skills. (experience)
- Passionate about developing world-class/innovative formal verification solutions. (experience)
- Exposure to CPU instruction-set architectures, memory consistency or cache coherence principles. (experience)
Responsibilities
- As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for:
- - Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification
- - Developing comprehensive formal verification test plan that includes unique security requirement verification
- - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture.
- - Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures
- - Developing and implementing re-usable and optimized formal models and verification code base
- - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Tags & Categories
Answer 10 quick questions to check your fit for Formal Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs