Job Description

Locations

• Santa Clara, California, United States 95050

Salary

Skills Required

• strategic engineeringintermediate
• physical designintermediate
• large chip integrationintermediate
• chip design from RTL to tapeoutintermediate
• chip architecture understandingintermediate
• PD construction and optimizationintermediate
• performance, power and Area (PPA) optimizationintermediate
• pioneering designs in latest technology nodesintermediate
• driving methodologies and best known methodsintermediate
• guidelines and checklists developmentintermediate
• execution drivingintermediate
• progress supervisionintermediate
• place and route engineeringintermediate
• goal setting and breakthroughsintermediate
• short and long-term planningintermediate
• dependencies understanding (top, STA, block PnR)intermediate
• design and flow issue resolutionintermediate
• potential solutions identificationintermediate

Required Qualifications

• BS + 3 years of relevant experience. (experience, 3 years)
• Experience with one or more of the following: floorplanning partitions, conducting route and placement flow experiments, reviewing static timing, and physical design verification flow results. (experience)

Preferred Qualifications

• We value ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff. (experience)
• Work with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback. (experience)
• Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs. (experience)
• Experience with multi-voltage, power gated, and power retention will be an advantage. (experience)
• Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset. (experience)
• Experience on integrating IP from both internal and external vendors and able to specify and drive IP requirements in the physical domain. (experience)
• Depth of expertise with large GPU designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies. (experience)
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal management. (experience)

Responsibilities

• - Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
• - Drive outstanding PD construction and optimization recipes for performance, power and Area (PPA).
• - Work on pioneering designs in the latest technology nodes.
• - Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress.
• - Drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR.
• - Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

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