Job Description

Locations

• Cambridge, England, United Kingdom CB2 3AX

Salary

Skills Required

• strategic engineeringintermediate
• hands-on technical workintermediate
• implementing complete chip designintermediate
• chip design from netlist to tapeoutintermediate
• physical designintermediate
• large chip integrationintermediate

Required Qualifications

• MSEE or equivalent is required. (experience)
• Deep experience with all aspects of ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration. (experience)

Preferred Qualifications

• Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. (experience)
• Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence. (experience)
• Depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. (experience)
• Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies. (experience)
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt. (experience)
• From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required. (experience)

Responsibilities

• This role requires a mix of strategic engineering along with hands-on, technical work, being responsible for implementing complete chip design from netlist to tapeout, and having hands on experience in physical design and large chip integration.
• • Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle.
• • Contribute to innovation with the physical design team, and develop methodologies and “best known methods” that will enable outstanding GPU design.
• • Develop PD guidelines and checklists and drive execution. Be the focal point for place and route integration at the top level • Plan short and long-term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
• • Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• • If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!

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