Job Description

Locations

• Santa Clara, California, United States 95050

Salary

Skills Required

• IP Integrationintermediate
• RTL Integrationintermediate
• Top-Level Assemblyintermediate
• Linting and Synthesisintermediate
• Build and Test Infrastructureintermediate
• Design Constraintsintermediate
• Timing Closureintermediate
• Functional Verification Supportintermediate
• Documentation and Reviewsintermediate
• ASIC designintermediate
• Integrate third-party or internal IP blocksintermediate
• Integrate CPUintermediate
• Integrate GPUintermediate
• Integrate memory controllersintermediate
• Integrate custom logicintermediate
• Manage and merge RTL codebasesintermediate
• Ensure connectivityintermediate
• Bus/interface protocolsintermediate
• AMBAintermediate
• AXIintermediate
• AHBintermediate
• Create and maintain top-level SoC RTLintermediate
• Create wrappersintermediate
• Create interconnectsintermediate
• Run and debug lintintermediate
• Run and debug CDCintermediate
• Run and debug RDCintermediate
• Logic synthesisintermediate
• Develop automated build systemsintermediate
• Develop regression systemsintermediate
• Define synthesis constraintsintermediate
• Define timing constraintsintermediate
• Validate SDC filesintermediate
• Achieve timing closureintermediate
• Work with physical design teamsintermediate
• Work with STA teamsintermediate
• Provide integration-level supportintermediate
• Simulation bring-upintermediate
• Debug verificationintermediate
• Create design documentsintermediate
• Maintain design documentsintermediate
• Participate in design reviewsintermediate

Required Qualifications

• Bachelor's Degree with +10 Years of Experience (experience, 10 years)

Preferred Qualifications

• Solid understanding of digital logic design and RTL development (SystemVerilog, Verilog). (experience)
• Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence). (experience)
• Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR). (experience)
• Knowledge of ASIC tool flows: lint, synthesis, CDC, DFT, STA. (experience)
• Strong scripting skills (Python, Perl, TCL, Shell) for automation. (experience)
• Good debugging and problem-solving skills. (experience)
• Excellent communication and cross-functional collaboration. (experience)

Responsibilities

• The ideal candidate will have experience in ASIC design with:
• • IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, GPU, memory controllers, custom logic) into a SoC.
• • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented.
• • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects.
• • Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.
• • Build and Test Infrastructure: Develop and maintain automated build and regression systems for integration.
• • Design Constraints: Define and validate synthesis and timing constraints (SDC files).
• • Timing Closure: Work closely with physical design and STA teams to achieve timing closure at top level.
• • Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up and debug.
• • Documentation and Reviews: Create and maintain design documents and participate in design reviews.

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