Mixed-Signal Clocking and Control RTL Design Engineer
Apple
Mixed-Signal Clocking and Control RTL Design Engineer
Job Description
At Apple, we are dedicated to designing products that enrich the lives of our users. Are you passionate about tackling challenges that have yet to be resolved? Do you thrive in innovative environments? We have a technically demanding Mixed-Signal Clocking and Control RTL Design position on our team. As a valued member of this group, you will have the opportunity to contribute to the development of groundbreaking products that will captivate and empower millions of Apple customers worldwide. In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RTL Designintermediate
- Mixed-Signal Clocking and Controlintermediate
- designing logic for oscillatorsintermediate
- designing logic for delay linesintermediate
- designing logic for phase interpolatorsintermediate
- working with multiple clocksintermediate
- complex clock domain crossingsintermediate
- signal processingintermediate
- control systemsintermediate
- analyzing control loopsintermediate
- gain analysisintermediate
- latency analysisintermediate
- transients analysisintermediate
- jitter analysisintermediate
- static timing analysisintermediate
- timing closureintermediate
- Lintintermediate
- CDCintermediate
- RDCintermediate
- working with system architectsintermediate
- design verificationintermediate
- crafting testsintermediate
- debugging testsintermediate
- post-silicon debugintermediate
- post-silicon analysisintermediate
Required Qualifications
- MS degree in technical discipline with minimum of 3 years of relevant experience. (experience, 3 years)
Preferred Qualifications
- Excellent knowledge of digital logic gates, clocking and state elements (experience)
- Excellent knowledge of writing synthesizable code in SystemVerilog (experience)
- Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools (experience)
- Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation (experience)
- Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators (experience)
- Prior experience working on clocking circuits such as PLLs/DLLs/CDRs (experience)
- Familiarity with DACs and oversampling modulators (experience)
- Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling (experience)
- Familiarity with the basics of digital signal processing and closed loop control (experience)
Responsibilities
- In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.
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Answer 10 quick questions to check your fit for Mixed-Signal Clocking and Control RTL Design Engineer @ Apple.
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Mixed-Signal Clocking and Control RTL Design Engineer
Apple
Mixed-Signal Clocking and Control RTL Design Engineer
Job Description
At Apple, we are dedicated to designing products that enrich the lives of our users. Are you passionate about tackling challenges that have yet to be resolved? Do you thrive in innovative environments? We have a technically demanding Mixed-Signal Clocking and Control RTL Design position on our team. As a valued member of this group, you will have the opportunity to contribute to the development of groundbreaking products that will captivate and empower millions of Apple customers worldwide. In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RTL Designintermediate
- Mixed-Signal Clocking and Controlintermediate
- designing logic for oscillatorsintermediate
- designing logic for delay linesintermediate
- designing logic for phase interpolatorsintermediate
- working with multiple clocksintermediate
- complex clock domain crossingsintermediate
- signal processingintermediate
- control systemsintermediate
- analyzing control loopsintermediate
- gain analysisintermediate
- latency analysisintermediate
- transients analysisintermediate
- jitter analysisintermediate
- static timing analysisintermediate
- timing closureintermediate
- Lintintermediate
- CDCintermediate
- RDCintermediate
- working with system architectsintermediate
- design verificationintermediate
- crafting testsintermediate
- debugging testsintermediate
- post-silicon debugintermediate
- post-silicon analysisintermediate
Required Qualifications
- MS degree in technical discipline with minimum of 3 years of relevant experience. (experience, 3 years)
Preferred Qualifications
- Excellent knowledge of digital logic gates, clocking and state elements (experience)
- Excellent knowledge of writing synthesizable code in SystemVerilog (experience)
- Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools (experience)
- Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation (experience)
- Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators (experience)
- Prior experience working on clocking circuits such as PLLs/DLLs/CDRs (experience)
- Familiarity with DACs and oversampling modulators (experience)
- Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling (experience)
- Familiarity with the basics of digital signal processing and closed loop control (experience)
Responsibilities
- In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.
Tags & Categories
Answer 10 quick questions to check your fit for Mixed-Signal Clocking and Control RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs