Mixed-Signal Model Verification Engineer
Apple
Mixed-Signal Model Verification Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and detail oriented Mixed-signal Behavioral Model Verification Engineer. If you are early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, come join the Apple mixed-signal silicon design team. In this position you will build a strong foundation in the working of full custom analog and high-speed digital circuits. You will work with experts in circuit design, behavioral modeling and design verification. You will gain expertise in hybrid simulation methods and various flows used to verify full custom designs. In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- detail orientedintermediate
- circuit designintermediate
- behavioral modelingintermediate
- design verificationintermediate
- hybrid simulation methodsintermediate
- SystemVerilogintermediate
- creating self-checking testbenchesintermediate
- functional testingintermediate
- creating assertionsintermediate
- formal logical equivalenceintermediate
- lintingintermediate
- timing checksintermediate
- automation of flowsintermediate
Required Qualifications
- Bachelor’s degree with minimum 3 years of relevant experience (experience, 3 years)
Preferred Qualifications
- Excellent knowledge of SystemVerilog and Assertions (experience)
- Ability to read custom circuit schematics and understand functionality (experience)
- Solid understanding of logic/SPICE simulations as well as SPICE/HDL co-simulations (experience)
- Excellent knowledge of digital logic gates, clocking and state elements (experience)
- Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators (experience)
- Familiarity of writing scripts in PERL/Python is a strong plus (experience)
- Familiarity with formal equivalence and Lint/CDC/RDC tools is a strong plus (experience)
Responsibilities
- In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.
Tags & Categories
Answer 10 quick questions to check your fit for Mixed-Signal Model Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs
Mixed-Signal Model Verification Engineer
Apple
Mixed-Signal Model Verification Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and detail oriented Mixed-signal Behavioral Model Verification Engineer. If you are early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, come join the Apple mixed-signal silicon design team. In this position you will build a strong foundation in the working of full custom analog and high-speed digital circuits. You will work with experts in circuit design, behavioral modeling and design verification. You will gain expertise in hybrid simulation methods and various flows used to verify full custom designs. In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- detail orientedintermediate
- circuit designintermediate
- behavioral modelingintermediate
- design verificationintermediate
- hybrid simulation methodsintermediate
- SystemVerilogintermediate
- creating self-checking testbenchesintermediate
- functional testingintermediate
- creating assertionsintermediate
- formal logical equivalenceintermediate
- lintingintermediate
- timing checksintermediate
- automation of flowsintermediate
Required Qualifications
- Bachelor’s degree with minimum 3 years of relevant experience (experience, 3 years)
Preferred Qualifications
- Excellent knowledge of SystemVerilog and Assertions (experience)
- Ability to read custom circuit schematics and understand functionality (experience)
- Solid understanding of logic/SPICE simulations as well as SPICE/HDL co-simulations (experience)
- Excellent knowledge of digital logic gates, clocking and state elements (experience)
- Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators (experience)
- Familiarity of writing scripts in PERL/Python is a strong plus (experience)
- Familiarity with formal equivalence and Lint/CDC/RDC tools is a strong plus (experience)
Responsibilities
- In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.
Tags & Categories
Answer 10 quick questions to check your fit for Mixed-Signal Model Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs