PHY RTL Design Engineer
Apple
PHY RTL Design Engineer
Job Description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs, including: Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy-efficient designintermediate
- RF/Analog architectureintermediate
- RF/Analog designintermediate
- Systems/PHY/MAC architectureintermediate
- Systems/PHY/MAC designintermediate
- VLSI/RTL designintermediate
- VLSI/RTL integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- signal processingintermediate
- writing specificationsintermediate
- defining Microarchitectureintermediate
- MATLABintermediate
- C system modelintermediate
- architecting area and powerintermediate
- efficient low latency designsintermediate
- scalabilities and flexibilitiesintermediate
- RTL logic designintermediate
- DV supportintermediate
- running tools for lintintermediate
- CDC/RDC clean designintermediate
- synthesisintermediate
- timing constraintsintermediate
- design of signal processing Wireless protocolsintermediate
Required Qualifications
- Bachelors degree and 3+ years of relevant industry experience. (experience, 3 years)
- Understanding of DSP fundamentals. (experience)
- Digital Communications knowledge. (experience)
- Proficiency in RTL Design. (experience)
Preferred Qualifications
- Familiarity with UVM DV environment and AI based efficiency improvement flows. (experience)
- Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications. (experience)
- Understanding of Decoders - Viterbi, LDPC, Polar. (experience)
- Understanding of Filter design, multi-radix implementation, and compromises. (experience)
- Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis. (experience)
- Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation. (experience)
- Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus. (experience)
- Background in computer architecture. (experience)
- Bus fabric, especially APB/AHB/AXI. (experience)
- Power management with multiple power domains. (experience)
- Ability to work well in a team and be productive under ambitious schedules. (experience)
- Should exhibit excellent interpersonal skills and be self-motivated and well-organized. (experience)
- Experience with FPGA and/or emulation platform desired. (experience)
- Excellent communication skills – both written, and oral. (experience)
Responsibilities
- Develop signal processing intensive design for wireless communication SoCs, including:
- Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
- RTL coding and verification for PHY modem development.
- Support banckend activities by reviewing the reports and appropriate adjustment of the design.
- Involve in the pre and post silicon bringup process.
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Answer 10 quick questions to check your fit for PHY RTL Design Engineer @ Apple.
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PHY RTL Design Engineer
Apple
PHY RTL Design Engineer
Job Description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs, including: Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy-efficient designintermediate
- RF/Analog architectureintermediate
- RF/Analog designintermediate
- Systems/PHY/MAC architectureintermediate
- Systems/PHY/MAC designintermediate
- VLSI/RTL designintermediate
- VLSI/RTL integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- signal processingintermediate
- writing specificationsintermediate
- defining Microarchitectureintermediate
- MATLABintermediate
- C system modelintermediate
- architecting area and powerintermediate
- efficient low latency designsintermediate
- scalabilities and flexibilitiesintermediate
- RTL logic designintermediate
- DV supportintermediate
- running tools for lintintermediate
- CDC/RDC clean designintermediate
- synthesisintermediate
- timing constraintsintermediate
- design of signal processing Wireless protocolsintermediate
Required Qualifications
- Bachelors degree and 3+ years of relevant industry experience. (experience, 3 years)
- Understanding of DSP fundamentals. (experience)
- Digital Communications knowledge. (experience)
- Proficiency in RTL Design. (experience)
Preferred Qualifications
- Familiarity with UVM DV environment and AI based efficiency improvement flows. (experience)
- Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications. (experience)
- Understanding of Decoders - Viterbi, LDPC, Polar. (experience)
- Understanding of Filter design, multi-radix implementation, and compromises. (experience)
- Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis. (experience)
- Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation. (experience)
- Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus. (experience)
- Background in computer architecture. (experience)
- Bus fabric, especially APB/AHB/AXI. (experience)
- Power management with multiple power domains. (experience)
- Ability to work well in a team and be productive under ambitious schedules. (experience)
- Should exhibit excellent interpersonal skills and be self-motivated and well-organized. (experience)
- Experience with FPGA and/or emulation platform desired. (experience)
- Excellent communication skills – both written, and oral. (experience)
Responsibilities
- Develop signal processing intensive design for wireless communication SoCs, including:
- Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
- RTL coding and verification for PHY modem development.
- Support banckend activities by reviewing the reports and appropriate adjustment of the design.
- Involve in the pre and post silicon bringup process.
Tags & Categories
Answer 10 quick questions to check your fit for PHY RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs