Job Description

Locations

• Cupertino, California, United States 95014

Salary

Skills Required

• leadershipintermediate
• influenceintermediate
• communicationintermediate
• physical design principlesintermediate
• audit vendor PD flows and methodologiesintermediate
• suggest improvements to methodologyintermediate
• optimize QoRintermediate
• work with internal teamsintermediate
• work with specialistsintermediate
• conduct design reviewsintermediate
• review PD reportsintermediate
• review STA reportsintermediate
• review SI reportsintermediate
• review electrical analysis reportsintermediate
• sign-off for tapeoutintermediate
• post tapeout supportintermediate
• work on ECOsintermediate
• debugintermediate
• adhere to standardsintermediate
• maintain professional relationshipsintermediate

Required Qualifications

• BS and 10+ years of experience in Physical Design. (experience, 10 years)
• Knowledge of digital design concepts. (experience)

Preferred Qualifications

• Experience leading physical design teams. (experience)
• Track record of having taped out a number of complex chips - from gates to GDS. (experience)
• Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques. (experience)
• In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification. (experience)
• Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech. (experience)
• Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing. (experience)
• Hands-on experience in Power and Signal Integrity analysis. (experience)
• Ability to debug and fix LVS, DRC, Antenna, ERC issues. (experience)
• Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc. (experience)
• Mixed signal SoC tapeouts involving multiple instances of analog IPs. (experience)
• Low power / leakage management methodology and techniques. (experience)
• Extraction and characterization of IP elements. (experience)

Responsibilities

• You will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community.
• We value your technical understanding of physical design principles. You will be responsible for ensuring the high quality of the chips and is expected to:
• •Audit vendor PD flows and methodologies for any holes and set up issues.
• •Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips.
• •Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals.
• •Work closely with specialists from other teams like the packaging, process etc. to resolve any issues in the project which are in an area closely related to PD.
• •Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work.
• •Review all the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval.
• •Provide post tapeout support to work on ECOs and debug, if required.
• •Adhere to a strict and consistent standard of operation across all vendors and projects.
• •Maintain a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.

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