Physical Synthesis CAD Engineer
Apple
Physical Synthesis CAD Engineer
Job Description
Do you want to directly impact the performance of every iPhone, iPad, and Mac? You'll push the boundaries of physical synthesis for Apple's cutting-edge processors, solving problems that determine whether our next-generation CPUs, GPUs, and NPUs can deliver breakthrough performance while maintaining industry-leading power efficiency. You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices. You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- physical synthesisintermediate
- developing implementation flowintermediate
- RTLintermediate
- GDS signoffintermediate
- innovative scriptsintermediate
- automationintermediate
- synthesis techniquesintermediate
- develop methodologiesintermediate
- develop toolsintermediate
- optimized flowsintermediate
- PPA optimizationintermediate
- validation flowsintermediate
- place-and-routeintermediate
- timing signoffintermediate
- EDA vendor collaborationintermediate
- custom solutionsintermediate
Required Qualifications
- Experience with TCL, Python or Perl scripting languages (experience)
- Minimum requirement of BS (experience)
Preferred Qualifications
- Experience with industry standard Synthesis tools such as Fusion Compiler or Genus (experience)
- Experience working with CAD Tools & flow (experience)
- Experience in CAD flow or FE methodology development (experience)
- Experience with Low Power implementation flows (UPF) is a plus (experience)
- Experience with logical equivalence tools such as Conformal LEC and/or Formality is a plus (experience)
- Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus (experience)
- Proficiency with TCL, Python or Perl scripting languages strongly preferred (experience)
Responsibilities
- You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation.
- As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices.
- You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices.
- Develop breakthrough physical synthesis techniques and validate them with full implementation flows (PNR, STA, power analysis)
- Apply advanced RTL optimization techniques to achieve substantial improvements in performance, power, and area (PPA)
- Partner with design teams to define optimal methodologies and flows, enabling them to achieve superior PPA results
- Create custom tools and ML-based methodologies for today's most challenging high-performance, low-power design problems
- Drive synthesis innovation that enables Apple's next-generation processor architectures
- Influence EDA vendor tool development by solving the hardest problems
- Deploy solutions across multiple critical Apple Silicon projects
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Answer 10 quick questions to check your fit for Physical Synthesis CAD Engineer @ Apple.
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~2 Minutes
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Physical Synthesis CAD Engineer
Apple
Physical Synthesis CAD Engineer
Job Description
Do you want to directly impact the performance of every iPhone, iPad, and Mac? You'll push the boundaries of physical synthesis for Apple's cutting-edge processors, solving problems that determine whether our next-generation CPUs, GPUs, and NPUs can deliver breakthrough performance while maintaining industry-leading power efficiency. You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices. You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- physical synthesisintermediate
- developing implementation flowintermediate
- RTLintermediate
- GDS signoffintermediate
- innovative scriptsintermediate
- automationintermediate
- synthesis techniquesintermediate
- develop methodologiesintermediate
- develop toolsintermediate
- optimized flowsintermediate
- PPA optimizationintermediate
- validation flowsintermediate
- place-and-routeintermediate
- timing signoffintermediate
- EDA vendor collaborationintermediate
- custom solutionsintermediate
Required Qualifications
- Experience with TCL, Python or Perl scripting languages (experience)
- Minimum requirement of BS (experience)
Preferred Qualifications
- Experience with industry standard Synthesis tools such as Fusion Compiler or Genus (experience)
- Experience working with CAD Tools & flow (experience)
- Experience in CAD flow or FE methodology development (experience)
- Experience with Low Power implementation flows (UPF) is a plus (experience)
- Experience with logical equivalence tools such as Conformal LEC and/or Formality is a plus (experience)
- Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus (experience)
- Proficiency with TCL, Python or Perl scripting languages strongly preferred (experience)
Responsibilities
- You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation.
- As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices.
- You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices.
- Develop breakthrough physical synthesis techniques and validate them with full implementation flows (PNR, STA, power analysis)
- Apply advanced RTL optimization techniques to achieve substantial improvements in performance, power, and area (PPA)
- Partner with design teams to define optimal methodologies and flows, enabling them to achieve superior PPA results
- Create custom tools and ML-based methodologies for today's most challenging high-performance, low-power design problems
- Drive synthesis innovation that enables Apple's next-generation processor architectures
- Influence EDA vendor tool development by solving the hardest problems
- Deploy solutions across multiple critical Apple Silicon projects
Tags & Categories
Answer 10 quick questions to check your fit for Physical Synthesis CAD Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs