PLL/Clocking Design Engineer
Apple
PLL/Clocking Design Engineer
Job Description
At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference. In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- collaborative problem-solvingintermediate
- continual learningintermediate
- developing frequency synthesizersintermediate
- expertise in Compute technologiesintermediate
- expertise in SoC technologiesintermediate
- expertise in SerDes technologiesintermediate
- expertise in Cellular technologiesintermediate
Required Qualifications
- BSEE with at least 3 years of relevant experience (experience, 3 years)
Preferred Qualifications
- Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc (experience)
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques. (experience)
- Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics. (degree)
- Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus. (experience)
- Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving. (experience)
- Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset. (experience)
- Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools. (experience)
Responsibilities
- In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
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Answer 10 quick questions to check your fit for PLL/Clocking Design Engineer @ Apple.
10 Questions
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PLL/Clocking Design Engineer
Apple
PLL/Clocking Design Engineer
Job Description
At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference. In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- collaborative problem-solvingintermediate
- continual learningintermediate
- developing frequency synthesizersintermediate
- expertise in Compute technologiesintermediate
- expertise in SoC technologiesintermediate
- expertise in SerDes technologiesintermediate
- expertise in Cellular technologiesintermediate
Required Qualifications
- BSEE with at least 3 years of relevant experience (experience, 3 years)
Preferred Qualifications
- Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc (experience)
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques. (experience)
- Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics. (degree)
- Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus. (experience)
- Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving. (experience)
- Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset. (experience)
- Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools. (experience)
Responsibilities
- In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Tags & Categories
Answer 10 quick questions to check your fit for PLL/Clocking Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs