PMU Design Verification Engineer (m/f/d)
Apple
PMU Design Verification Engineer (m/f/d)
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will involve verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role you will develop verification plans in coordination with design leads and architects. Your responsibilities will include: - Building and maintaining verification test bench components and environments - Generate directed and constrained random tests - Run simulations and debug design and environment issues - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes - Craft automated verification flows for block and chip level verification - Apply knowledge of hardware description languages, hardware verification languages (SystemVerilog), methodology (UVM/OVM), and logic simulators to verify complex designs - Work with other block and chip level engineers to ensure a flawless verification flow
Locations
- Munich, Bavaria-Bayern, Germany 80335
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- results-orientedintermediate
- highly committedintermediate
- design verification methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus developmentintermediate
- checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freezeintermediate
- sign-off for tape-outintermediate
- developing verification plansintermediate
- building verification test bench componentsintermediate
- maintaining verification environmentsintermediate
- generating directed testsintermediate
- generating constrained random testsintermediate
- running simulationsintermediate
- debugging design issuesintermediate
- debugging environment issuesintermediate
- building functional coverage pointsintermediate
- analyzing coverageintermediate
- improving test environmentintermediate
- crafting automated verification flowsintermediate
- block level verificationintermediate
- chip level verificationintermediate
- knowledge of hardware description languagesintermediate
- knowledge of hardware verification languages (SystemVerilog)intermediate
- methodology (UVM/OVM)intermediate
- knowledge of logic simulatorsintermediate
- verifying complex designsintermediate
- collaboration with Digital and Analog Design engineersintermediate
Required Qualifications
- Advanced knowledge of SystemVerilog and UVM (experience)
- Experience developing scalable and portable test-benches (experience)
- Experience with constrained random verification environments (experience)
- Experience defining coverage space, writing coverage model, analyzing results (experience)
- Experience with Assertion Based Verification (experience)
- Knowledge of Object Oriented Programming (experience)
- MS/BS in Computer Science or Electrical Engineering or equivalent (experience)
- Fluency in English language is required (experience)
Preferred Qualifications
- Basic knowledge of mixed signal verification (experience)
- Experience in Formal Verification (experience)
- Excellent communication and interpersonal skills combined with the ability to collaborate (experience)
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. (experience)
- We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. (experience)
Responsibilities
- In this role you will develop verification plans in coordination with design leads and architects.
- Your responsibilities will include:
- - Building and maintaining verification test bench components and environments
- - Generate directed and constrained random tests
- - Run simulations and debug design and environment issues
- - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes
- - Craft automated verification flows for block and chip level verification
- - Apply knowledge of hardware description languages, hardware verification languages (SystemVerilog), methodology (UVM/OVM), and logic simulators to verify complex designs
- - Work with other block and chip level engineers to ensure a flawless verification flow
Tags & Categories
Answer 10 quick questions to check your fit for PMU Design Verification Engineer (m/f/d) @ Apple.
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~2 Minutes
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PMU Design Verification Engineer (m/f/d)
Apple
PMU Design Verification Engineer (m/f/d)
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will involve verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. In this role you will develop verification plans in coordination with design leads and architects. Your responsibilities will include: - Building and maintaining verification test bench components and environments - Generate directed and constrained random tests - Run simulations and debug design and environment issues - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes - Craft automated verification flows for block and chip level verification - Apply knowledge of hardware description languages, hardware verification languages (SystemVerilog), methodology (UVM/OVM), and logic simulators to verify complex designs - Work with other block and chip level engineers to ensure a flawless verification flow
Locations
- Munich, Bavaria-Bayern, Germany 80335
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- results-orientedintermediate
- highly committedintermediate
- design verification methodologyintermediate
- test-plan developmentintermediate
- verification environment developmentintermediate
- stimulus developmentintermediate
- checkers developmentintermediate
- test-writingintermediate
- debugintermediate
- coverage analysisintermediate
- sign-off for RTL freezeintermediate
- sign-off for tape-outintermediate
- developing verification plansintermediate
- building verification test bench componentsintermediate
- maintaining verification environmentsintermediate
- generating directed testsintermediate
- generating constrained random testsintermediate
- running simulationsintermediate
- debugging design issuesintermediate
- debugging environment issuesintermediate
- building functional coverage pointsintermediate
- analyzing coverageintermediate
- improving test environmentintermediate
- crafting automated verification flowsintermediate
- block level verificationintermediate
- chip level verificationintermediate
- knowledge of hardware description languagesintermediate
- knowledge of hardware verification languages (SystemVerilog)intermediate
- methodology (UVM/OVM)intermediate
- knowledge of logic simulatorsintermediate
- verifying complex designsintermediate
- collaboration with Digital and Analog Design engineersintermediate
Required Qualifications
- Advanced knowledge of SystemVerilog and UVM (experience)
- Experience developing scalable and portable test-benches (experience)
- Experience with constrained random verification environments (experience)
- Experience defining coverage space, writing coverage model, analyzing results (experience)
- Experience with Assertion Based Verification (experience)
- Knowledge of Object Oriented Programming (experience)
- MS/BS in Computer Science or Electrical Engineering or equivalent (experience)
- Fluency in English language is required (experience)
Preferred Qualifications
- Basic knowledge of mixed signal verification (experience)
- Experience in Formal Verification (experience)
- Excellent communication and interpersonal skills combined with the ability to collaborate (experience)
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. (experience)
- We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. (experience)
Responsibilities
- In this role you will develop verification plans in coordination with design leads and architects.
- Your responsibilities will include:
- - Building and maintaining verification test bench components and environments
- - Generate directed and constrained random tests
- - Run simulations and debug design and environment issues
- - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes
- - Craft automated verification flows for block and chip level verification
- - Apply knowledge of hardware description languages, hardware verification languages (SystemVerilog), methodology (UVM/OVM), and logic simulators to verify complex designs
- - Work with other block and chip level engineers to ensure a flawless verification flow
Tags & Categories
Answer 10 quick questions to check your fit for PMU Design Verification Engineer (m/f/d) @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs