Job Description

Locations

• Nabern, Baden-Wurttemberg, Germany

Salary

Skills Required

• passion for innovationintermediate
• dedicationintermediate
• collaborativeintermediate
• solution-orientedintermediate
• design verificationintermediate
• establishing design verification methodologyintermediate
• test-plan developmentintermediate
• verification environment developmentintermediate
• stimulus developmentintermediate
• checkers developmentintermediate
• test-writingintermediate
• debugintermediate
• coverageintermediate
• sign-off for RTL freezeintermediate
• sign-off for tape-outintermediate

Required Qualifications

• Currently pursuing a BS, or MS in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field. (experience)
• At the end of the internship, you must return to school to continue your education or the internship must be the last requirement for you to graduate. (experience)
• English language fluency (written and verbal) and collaboration skills (experience)
• Excellent communication and interpersonal skills, combined with the ability to collaborate (experience)
• Ability to work well on a team, take ownership and motivate self and others (experience)
• Knowledge of SystemVerilog and UVM (experience)
• Experience with Python, Perl or TCL (experience)
• Good knowledge of Object Oriented Programming (experience)
• Available for 6 months or more (experience)

Preferred Qualifications

• Experience developing scalable and portable test-benches (experience)
• Good understanding of digital design and basic knowledge of mixed signal verification (experience)

Responsibilities

• The Silicon Engineering Group is responsible for developing cutting edge chips that can be found in all of your favourite Apple products. Our power management design team in Nabern (close to Stuttgart) has a unique opportunity for a motivated, collaborative, and solution-oriented intern to actively contribute to our chip development. We are looking for a Design Verification Intern in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with our team of Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
• You will develop verification plans in coordination with design leads and architects.
• You'll be responsible for building and maintaining verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• Craft automated verification flows for block and chip level verification.
• Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs.
• Work with other block and core level engineers to ensure a flawless verification flow.
• Work with Assertion Based Verification

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