Job Description

Locations

• Cupertino, California, United States 95014

Salary

Skills Required

• transistor level power ERC sign-offintermediate
• power intent-UPF implementationintermediate
• UPF verificationintermediate
• ASIC designintermediate
• SOC designintermediate
• mixed signal designsintermediate
• full-chip power ERC sign-offintermediate
• Mixed signal IP power ERCintermediate
• power intent verificationintermediate
• static and dynamic checking methodologiesintermediate
• power ERC framework developmentintermediate
• power intent checking flowsintermediate
• power ERC sign-off for tape-outintermediate
• debugging power ERC and power intent flow issuesintermediate
• collaboration with CAD and physical design verification teamsintermediate

Required Qualifications

• A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience (experience, 3 years)

Preferred Qualifications

• We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition. (experience)
• Experience in ASIC design flows and custom IP design flows. (experience)
• Familiar with Caliber based ERC flows. (experience)
• Familiar with power intent definition, implementation and verification flows. (experience)
• Knowledge of scripting languages like, Tcl, Perl and Python. (experience)
• Familiar with of power analysis and optimization methods. (experience)
• Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking) (experience)
• Strong communication skills are a pre-requisite as you will collaborate with a lot of different groups. (experience)

Responsibilities

• Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly.
• You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including:
• - Drive Mixed signal IP power ERC and power intent verification.
• - Drive coverage of power intent across static and dynamic checking methodologies.
• - Define and develop power ERC framework for new projects.
• - Bring up power intent checking flows on new projects.
• - Drive power intent & power ERC sign-off for tape-out.
• - Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues.

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