RFIC Layout Engineer
Apple
RFIC Layout Engineer
Job Description
Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding `team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block-level and top-level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. - Top-level layout integration and verification, schedule management.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy efficient designintermediate
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- Block level layoutintermediate
- Top-level layoutintermediate
- full verification flowintermediate
- extractionintermediate
- DRCintermediate
- LVSintermediate
- DFM checkingintermediate
- floorplanningintermediate
- power/gnd routingintermediate
- electromigrationintermediate
- signal path checkintermediate
- differential matchingintermediate
- IQ matchingintermediate
- signal couplingintermediate
- Top-level layout integrationintermediate
- schedule managementintermediate
- collaborationintermediate
- teamworkintermediate
- innovationintermediate
Required Qualifications
- 8+ year minimum related experience required (experience, 8 years)
- Good understanding of RC delay, electromigration, and coupling. (experience)
- Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. (experience)
- Excellent communication skills and ability to work with multi-functional teams. (experience)
Preferred Qualifications
- Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing. (experience)
- Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience). (experience)
- Solid understanding of RC delay, electromigration, and coupling. (experience)
- Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc. (experience)
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology. (experience)
- Extensive knowledge of CADENCE layout tools. (experience)
- Capability to lead other layout engineers for top-level integration. (experience)
- Scripting skills in PERL or SKILL are a plus. (experience)
Responsibilities
- Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.
- - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
- - Co-work with designers on block-level and top-level floorplanning.
- - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
- - Top-level layout integration and verification, schedule management.
- As a RF layout engineer, you will be responsible for:
- Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
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Answer 10 quick questions to check your fit for RFIC Layout Engineer @ Apple.
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RFIC Layout Engineer
Apple
RFIC Layout Engineer
Job Description
Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding `team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block-level and top-level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. - Top-level layout integration and verification, schedule management.
Locations
- Irvine, California, United States 92602
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy efficient designintermediate
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- Block level layoutintermediate
- Top-level layoutintermediate
- full verification flowintermediate
- extractionintermediate
- DRCintermediate
- LVSintermediate
- DFM checkingintermediate
- floorplanningintermediate
- power/gnd routingintermediate
- electromigrationintermediate
- signal path checkintermediate
- differential matchingintermediate
- IQ matchingintermediate
- signal couplingintermediate
- Top-level layout integrationintermediate
- schedule managementintermediate
- collaborationintermediate
- teamworkintermediate
- innovationintermediate
Required Qualifications
- 8+ year minimum related experience required (experience, 8 years)
- Good understanding of RC delay, electromigration, and coupling. (experience)
- Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. (experience)
- Excellent communication skills and ability to work with multi-functional teams. (experience)
Preferred Qualifications
- Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing. (experience)
- Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience). (experience)
- Solid understanding of RC delay, electromigration, and coupling. (experience)
- Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc. (experience)
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology. (experience)
- Extensive knowledge of CADENCE layout tools. (experience)
- Capability to lead other layout engineers for top-level integration. (experience)
- Scripting skills in PERL or SKILL are a plus. (experience)
Responsibilities
- Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.
- - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
- - Co-work with designers on block-level and top-level floorplanning.
- - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
- - Top-level layout integration and verification, schedule management.
- As a RF layout engineer, you will be responsible for:
- Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
Tags & Categories
Answer 10 quick questions to check your fit for RFIC Layout Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs