RTL Design Engineer
Apple
RTL Design Engineer
Job Description
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- IP architectureintermediate
- IP designintermediate
- IP verificationintermediate
- SystemVerilogintermediate
- SV simulationsintermediate
- SVA formal verificationintermediate
- Lintintermediate
- CDCintermediate
- RDCintermediate
- DFTintermediate
- Debugintermediate
- formal verificationintermediate
- quality checkersintermediate
- providing constraints and waiversintermediate
- supporting DV simulation teamintermediate
- supporting bring-up teamsintermediate
- documentationintermediate
- example codeintermediate
- integration notesintermediate
- giving presentationsintermediate
- collaborating with cross-functional teamsintermediate
- thriving in fast-paced environmentintermediate
- thriving during crisis timesintermediate
Required Qualifications
- BS and a minimum of 10 years relevant industry experience (experience, 10 years)
- Fluency in RTL design using SystemVerilog (experience)
- Experience designing for one or more AMBA protocols - AHB, AXI, APB (experience)
- Working knowledge of synthesis and static timing analysis (experience)
- Comfortable with clock domain crossings as well as CDC/RDC checking tools (experience)
Preferred Qualifications
- Fluency in SystemVerilog Assertions (experience)
- Background in low power design (experience)
- Understanding of embedded software design (experience)
- Experience in diagramming architectures and presenting designs to integration/software teams (experience)
Responsibilities
- In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.
- Architecting and documenting new modules
- Coding designs in SystemVerilog
- Running FV & DV at module level
- Checking your design with industry standard static tools such as LINT, CDC, RDC
- Analyzing and optimizing area, timing, and power
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RTL Design Engineer
Apple
RTL Design Engineer
Job Description
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RF/Analog architecture and designintermediate
- Systems/PHY/MAC architecture and designintermediate
- VLSI/RTL design and integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- IP architectureintermediate
- IP designintermediate
- IP verificationintermediate
- SystemVerilogintermediate
- SV simulationsintermediate
- SVA formal verificationintermediate
- Lintintermediate
- CDCintermediate
- RDCintermediate
- DFTintermediate
- Debugintermediate
- formal verificationintermediate
- quality checkersintermediate
- providing constraints and waiversintermediate
- supporting DV simulation teamintermediate
- supporting bring-up teamsintermediate
- documentationintermediate
- example codeintermediate
- integration notesintermediate
- giving presentationsintermediate
- collaborating with cross-functional teamsintermediate
- thriving in fast-paced environmentintermediate
- thriving during crisis timesintermediate
Required Qualifications
- BS and a minimum of 10 years relevant industry experience (experience, 10 years)
- Fluency in RTL design using SystemVerilog (experience)
- Experience designing for one or more AMBA protocols - AHB, AXI, APB (experience)
- Working knowledge of synthesis and static timing analysis (experience)
- Comfortable with clock domain crossings as well as CDC/RDC checking tools (experience)
Preferred Qualifications
- Fluency in SystemVerilog Assertions (experience)
- Background in low power design (experience)
- Understanding of embedded software design (experience)
- Experience in diagramming architectures and presenting designs to integration/software teams (experience)
Responsibilities
- In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.
- Architecting and documenting new modules
- Coding designs in SystemVerilog
- Running FV & DV at module level
- Checking your design with industry standard static tools such as LINT, CDC, RDC
- Analyzing and optimizing area, timing, and power
Tags & Categories
Answer 10 quick questions to check your fit for RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs