RTL Design Engineer
Apple
RTL Design Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, you will have the opportunity to specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side). In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Locations
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RTL Designintermediate
- mixed-signal circuits designintermediate
- embedded micro-controller designintermediate
- DFT architecturesintermediate
- low power designintermediate
- RTL codingintermediate
- design verificationintermediate
- RTL assertionsintermediate
- debugging codeintermediate
- pre-silicon power analysisintermediate
- clock domain crossingintermediate
- reset domain crossingintermediate
- UPFintermediate
- lab bring-upintermediate
- writing test scriptsintermediate
- analyzing lab dataintermediate
- proposing experimentsintermediate
Required Qualifications
- BS degree in technical discipline with minimum 10 years of relevant experience. (experience, 10 years)
Preferred Qualifications
- Deep knowledge of mixed signal concepts (experience)
- Deep knowledge of RTL design fundamentals (control and data path). (experience)
- Deep knowledge of Verilog and SystemVerilog. (experience)
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers). (experience)
- Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test). (experience)
- Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques. (experience)
- Deep knowledge of scripting languages. Perl and Python are plusses. (experience)
- Deep knowledge of Algorithm developments. (experience)
- Strong communication and presentation skills. (experience)
- SERDES architecture knowledge is a plus. (experience)
Responsibilities
- In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Tags & Categories
Answer 10 quick questions to check your fit for RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs
RTL Design Engineer
Apple
RTL Design Engineer
Job Description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, you will have the opportunity to specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side). In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Locations
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- RTL Designintermediate
- mixed-signal circuits designintermediate
- embedded micro-controller designintermediate
- DFT architecturesintermediate
- low power designintermediate
- RTL codingintermediate
- design verificationintermediate
- RTL assertionsintermediate
- debugging codeintermediate
- pre-silicon power analysisintermediate
- clock domain crossingintermediate
- reset domain crossingintermediate
- UPFintermediate
- lab bring-upintermediate
- writing test scriptsintermediate
- analyzing lab dataintermediate
- proposing experimentsintermediate
Required Qualifications
- BS degree in technical discipline with minimum 10 years of relevant experience. (experience, 10 years)
Preferred Qualifications
- Deep knowledge of mixed signal concepts (experience)
- Deep knowledge of RTL design fundamentals (control and data path). (experience)
- Deep knowledge of Verilog and SystemVerilog. (experience)
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers). (experience)
- Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test). (experience)
- Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques. (experience)
- Deep knowledge of scripting languages. Perl and Python are plusses. (experience)
- Deep knowledge of Algorithm developments. (experience)
- Strong communication and presentation skills. (experience)
- SERDES architecture knowledge is a plus. (experience)
Responsibilities
- In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Tags & Categories
Answer 10 quick questions to check your fit for RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs