SerDes Senior Circuit Design Engineer
Apple
SerDes Senior Circuit Design Engineer
Job Description
We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple’s world-leading system-on-chip (SOC). In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create, execute and drive state-of-the-art IPs key to Apple’s products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency. If you have strong fundamentals and a track record of tackling technical challenges, If you are passionate about learning new skills and improving the value of your work, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and tackle problems, We invite you to join and grow with our team. You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA). You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Analog Mixed-Signal designintermediate
- high-speed SerDes designintermediate
- wireline transceiver developmentintermediate
- IP development for SOCintermediate
- cross-functional team collaborationintermediate
- circuit topology evaluationintermediate
- Rx designintermediate
- CDR designintermediate
- Tx designintermediate
- bias generator designintermediate
- high-speed clock generationintermediate
- low-jitter distributionintermediate
- phase interpolator designintermediate
- DLL designintermediate
- VCO designintermediate
- LDO designintermediate
- PPA optimizationintermediate
- block-level specification creationintermediate
- mixed-signal implementationintermediate
- behavioral modelingintermediate
- architecture discussionsintermediate
- SIPI discussionsintermediate
- packaging discussionsintermediate
- board design discussionsintermediate
- DFT discussionsintermediate
- ESD discussionsintermediate
- SOC team collaborationintermediate
- IP quality assuranceintermediate
- progress communicationintermediate
- idea discussionintermediate
- problem-solvingintermediate
- innovationintermediate
- attention to detailintermediate
- big-picture thinkingintermediate
- learning new skillsintermediate
Required Qualifications
- BSEE with 10+ years of proven experience. (experience, 10 years)
Preferred Qualifications
- The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links. (experience)
- Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters (experience)
- Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques (experience)
- Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops) (experience)
- Proven track record of working with system and architecture teams to drive block-level and IP requirements (experience)
- Proven track record of working with large teams and guiding junior engineers (experience)
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts (experience)
- Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 64-100+ Gbps NRZ and PAM applications (experience)
- Experience with EQ adaptation methods and circuit interactions to improve PPA (experience)
- Solid understanding of CDR architectures and implementations (experience)
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS) (experience)
- Hands-on experience to drive lab testing, debug and data analysis (experience)
- Hands-on experience in advanced CMOS technologies, design with FinFet technology (experience)
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization (experience)
- Experience in the following areas is a plus (experience)
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime) (experience)
- Concepts of IP delivery and quality checks (experience)
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired (experience)
- Skills in scripting and automation to enhance efficiency are highly desirable (experience)
Responsibilities
- You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
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SerDes Senior Circuit Design Engineer
Apple
SerDes Senior Circuit Design Engineer
Job Description
We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple’s world-leading system-on-chip (SOC). In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create, execute and drive state-of-the-art IPs key to Apple’s products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency. If you have strong fundamentals and a track record of tackling technical challenges, If you are passionate about learning new skills and improving the value of your work, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and tackle problems, We invite you to join and grow with our team. You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA). You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Analog Mixed-Signal designintermediate
- high-speed SerDes designintermediate
- wireline transceiver developmentintermediate
- IP development for SOCintermediate
- cross-functional team collaborationintermediate
- circuit topology evaluationintermediate
- Rx designintermediate
- CDR designintermediate
- Tx designintermediate
- bias generator designintermediate
- high-speed clock generationintermediate
- low-jitter distributionintermediate
- phase interpolator designintermediate
- DLL designintermediate
- VCO designintermediate
- LDO designintermediate
- PPA optimizationintermediate
- block-level specification creationintermediate
- mixed-signal implementationintermediate
- behavioral modelingintermediate
- architecture discussionsintermediate
- SIPI discussionsintermediate
- packaging discussionsintermediate
- board design discussionsintermediate
- DFT discussionsintermediate
- ESD discussionsintermediate
- SOC team collaborationintermediate
- IP quality assuranceintermediate
- progress communicationintermediate
- idea discussionintermediate
- problem-solvingintermediate
- innovationintermediate
- attention to detailintermediate
- big-picture thinkingintermediate
- learning new skillsintermediate
Required Qualifications
- BSEE with 10+ years of proven experience. (experience, 10 years)
Preferred Qualifications
- The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links. (experience)
- Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters (experience)
- Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques (experience)
- Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops) (experience)
- Proven track record of working with system and architecture teams to drive block-level and IP requirements (experience)
- Proven track record of working with large teams and guiding junior engineers (experience)
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts (experience)
- Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 64-100+ Gbps NRZ and PAM applications (experience)
- Experience with EQ adaptation methods and circuit interactions to improve PPA (experience)
- Solid understanding of CDR architectures and implementations (experience)
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS) (experience)
- Hands-on experience to drive lab testing, debug and data analysis (experience)
- Hands-on experience in advanced CMOS technologies, design with FinFet technology (experience)
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization (experience)
- Experience in the following areas is a plus (experience)
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime) (experience)
- Concepts of IP delivery and quality checks (experience)
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired (experience)
- Skills in scripting and automation to enhance efficiency are highly desirable (experience)
Responsibilities
- You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
Tags & Categories
Answer 10 quick questions to check your fit for SerDes Senior Circuit Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs